PIC18F2331/2431/4331/4431
14.2 Timer2 Interrupt
14.3 Output of TMR2
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match) pro-
vides the input for the 4-bit output counter/postscaler.
This counter generates the TMR2 match interrupt flag
which is latched in TMR2IF (PIR1<1>).
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode. Timer2 can be optionally
used as the shift clock source for the SSP module
operating in SPI mode.
The interrupt is enabled by setting the TMR2 Match
Interrupt Enable bit, TMR2IE (PIE1<1>). A range of
16 postscale options (from 1:1 through 1:16 inclusive)
can be selected with the postscaler control bits,
T2OUTPS<3:0> (T2CON<6:3>).
For additional information, see Section 19.0
“Synchronous Serial Port (SSP) Module”.
FIGURE 14-1:
TIMER2 BLOCK DIAGRAM
4
1:1 to 1:16
Set TMR2IF
Postscaler
T2OUTPS<3:0>
T2CKPS<1:0>
2
TMR2 Output
(to PWM or SSP)
TMR2/PR2
Match
Reset
1:1, 1:4, 1:16
Prescaler
PR2
FOSC/4
TMR2
Comparator
8
8
8
Internal Data Bus
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Reset Values
on Page:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
TXIF
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF INT0IF
RBIF
54
57
57
57
55
55
55
PIR1
—
—
—
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
CCP1IP TMR2IP TMR1IP
PIE1
TXIE
TXIP
IPR1
TMR2
T2CON
PR2
Timer2 Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
2010 Microchip Technology Inc.
DS39616D-page 137
MICROCHIP [ MICROCHIP ]
