欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4431-I/P的Datasheet PDF文件第132页浏览型号PIC18F4431-I/P的Datasheet PDF文件第133页浏览型号PIC18F4431-I/P的Datasheet PDF文件第134页浏览型号PIC18F4431-I/P的Datasheet PDF文件第135页浏览型号PIC18F4431-I/P的Datasheet PDF文件第137页浏览型号PIC18F4431-I/P的Datasheet PDF文件第138页浏览型号PIC18F4431-I/P的Datasheet PDF文件第139页浏览型号PIC18F4431-I/P的Datasheet PDF文件第140页  
PIC18F2331/2431/4331/4431  
14.1 Timer2 Operation  
14.0 TIMER2 MODULE  
Timer2 can be used as the PWM time base for the  
PWM mode of the CCP module. The TMR2 register is  
readable and writable, and is cleared on any device  
Reset. The input clock (FOSC/4) has a prescale option  
of 1:1, 1:4 or 1:16, selected by control bits,  
T2CKPS<1:0> (T2CON<1:0>). The match output of  
TMR2 goes through a 4-bit postscaler (which gives a  
1:1 to 1:16 scaling inclusive) to generate a TMR2  
interrupt, latched in flag bit, TMR2IF (PIR1<1>).  
The Timer2 module has the following features:  
• 8-bit Timer register (TMR2)  
• 8-bit Period register (PR2)  
• Readable and writable (both registers)  
• Software programmable prescaler (1:1, 1:4, 1:16)  
• Software programmable postscaler (1:1 to 1:16)  
• Interrupt on TMR2 match with PR2  
• SSP module optional use of TMR2 output to  
generate clock shift  
The TMR2 and PR2 registers are both directly readable  
and writable. The TMR2 register is cleared on any  
device Reset, while the PR2 register initializes at FFh.  
Timer2 has a control register, shown in Register 14-1.  
TMR2 can be shut off by clearing control bit, TMR2ON  
(T2CON<2>), to minimize power consumption.  
Figure 14-1 is a simplified block diagram of the Timer2  
module. Register 14-1 shows the Timer2 Control  
register. The prescaler and postscaler selection of  
Timer2 are controlled by this register.  
The prescaler and postscaler counters are cleared  
when any of the following occurs:  
• A write to the TMR2 register  
• A write to the T2CON register  
• Any device Reset (Power-on Reset, MCLR Reset,  
Watchdog Timer Reset or Brown-out Reset)  
TMR2 is not cleared when T2CON is written.  
REGISTER 14-1: T2CON: TIMER2 CONTROL REGISTER  
U-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
TOUTPS3  
TOUTPS2  
TOUTPS1  
TOUTPS0  
TMR2ON  
T2CKPS1  
T2CKPS0  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
Unimplemented: Read as ‘0’  
bit 6-3  
TOUTPS<3:0>: Timer2 Output Postscale Select bits  
0000= 1:1 Postscale  
0001= 1:2 Postscale  
1111= 1:16 Postscale  
bit 2  
TMR2ON: Timer2 On bit  
1= Timer2 is on  
0= Timer2 is off  
bit 1-0  
T2CKPS<1:0>: Timer2 Clock Prescale Select bits  
00= Prescaler is 1  
01= Prescaler is 4  
1x= Prescaler is 16  
DS39616D-page 136  
2010 Microchip Technology Inc.  
 复制成功!