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PIC18F4431-I/PT 参数 Datasheet PDF下载

PIC18F4431-I/PT图片预览
型号: PIC18F4431-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
10.3 PIE Registers  
The PIE registers contain the individual enable bits for  
the peripheral interrupts. Due to the number of peripheral  
interrupt sources, there are three Peripheral Interrupt  
Enable Registers (PIE1, PIE2 and PIE3). When  
IPEN = 0, the PEIE bit must be set to enable any of these  
peripheral interrupts.  
REGISTER 10-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1  
U-0  
R/W-0  
ADIE  
R/W-0  
RCIE  
R/W-0  
TXIE  
R/W-0  
SSPIE  
R/W-0  
R/W-0  
R/W-0  
CCP1IE  
TMR2IE  
TMR1IE  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
bit 6  
Unimplemented: Read as ‘0’  
ADIE: A/D Converter Interrupt Enable bit  
1= Enables the A/D interrupt  
0= Disables the A/D interrupt  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
RCIE: EUSART Receive Interrupt Enable bit  
1= Enables the EUSART receive interrupt  
0= Disables the EUSART receive interrupt  
TXIE: EUSART Transmit Interrupt Enable bit  
1= Enables the EUSART transmit interrupt  
0= Disables the EUSART transmit interrupt  
SSPIE: Synchronous Serial Port Interrupt Enable bit  
1= Enables the SSP interrupt  
0= Disables the SSP interrupt  
CCP1IE: CCP1 Interrupt Enable bit  
1= Enables the CCP1 interrupt  
0= Disables the CCP1 interrupt  
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit  
1= Enables the TMR2 to PR2 match interrupt  
0= Disables the TMR2 to PR2 match interrupt  
TMR1IE: TMR1 Overflow Interrupt Enable bit  
1= Enables the TMR1 overflow interrupt  
0= Disables the TMR1 overflow interrupt  
2010 Microchip Technology Inc.  
DS39616D-page 105  
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