PIC18F2220/2320/4220/4320
19.1 A/D Acquisition Requirements
19.2 A/D VREF+ and VREF- References
For the A/D converter to meet its specified accuracy, the
Charge Holding Capacitor (CHOLD) must be allowed to
fully charge to the input channel voltage level. The ana-
log input model is shown in Figure 19-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD). The source imped-
ance affects the offset voltage at the analog input (due to
pin leakage current). The maximum recommended
impedance for analog sources is 2.5 kΩ. After the
analog input channel is selected (changed), the channel
must be sampled for at least the minimum acquisition
time before starting a conversion.
If external voltage references are used instead of the
internal AVDD and AVSS sources, the source imped-
ance of the VREF+ and VREF- voltage sources must be
considered. During acquisition, currents supplied by
these sources are insignificant. However, during con-
version, the A/D module sinks and sources current
through the reference sources.
In order to maintain the A/D accuracy, the voltage ref-
erence source impedances should be kept low to
reduce voltage changes. These voltage changes occur
as reference currents flow through the reference
source impedance. The maximum recommended
impedance of the VREF+ and VREF- external
reference voltage sources is 75Ω.
Note:
When the conversion is started, the holding
capacitor is disconnected from the input pin.
Note:
When using external references, the
source impedance of the external voltage
references must be less than 75Ω in order
to achieve the specified ADC resolution. A
higher reference source impedance will
increase the ADC offset and gain errors.
Resistive voltage dividers will not provide a
low enough source impedance. To ensure
the best possible ADC performance, exter-
nal VREF inputs should be buffered with an
op amp or other low-impedance circuit.
To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 19-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is based
on the following application system assumptions:
CHOLD
RS
Conversion Error
VDD
Temperature
VHOLD
=
=
≤
=
=
=
120 pF
2.5 kΩ
1/2 LSb
5V → Rss = 7 kΩ
50°C (system max.)
0V @ time = 0
EQUATION 19-1: ACQUISITION TIME
TACQ
=
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
EQUATION 19-2: MINIMUM A/D HOLDING CAPACITOR
VHOLD
or
=
(VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))
)
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/2048)
EXAMPLE 19-1:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ
TAMP
TCOFF
=
=
=
TAMP + TC + TCOFF
5 µs
(Temp – 25°C)(0.05 µs/°C)
(50°C – 25°C)(0.05 µs/°C)
1.25 µs
Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs.
TC
–
-(CHOLD)(RIC + RSS + RS) ln(1/2047) µs
-(120 pF) (1 kΩ + 7 kΩ + 2.5 kΩ) ln(0.0004883) µs
9.61 µs
TACQ
=
5 µs + 1.25 µs + 9.61 µs
12.86 µs
DS39599C-page 216
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
