PIC18F2220/2320/4220/4320
desired location). The appropriate analog input chan-
19.8 Use of the CCP2 Trigger
nel must be selected and the minimum acquisition
period is either timed by the user or an appropriate
TACQ time, selected before the “special event trigger”,
sets the GO/DONE bit (starts a conversion).
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automati-
cally repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
TABLE 19-2: SUMMARY OF A/D REGISTERS
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000 0000 0000
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PSPIF
PSPIE
ADIF
ADIE
ADIP
CMIF
CMIE
CMIP
RCIF
RCIE
RCIP
—
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
SSPIF CCP1IF
SSPIE CCP1IE
SSPIP CCP1IP
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
CCP2IF 00-0 0000 00-0 0000
CCP2IE 00-0 0000 00-0 0000
CCP2IP 11-1 1111 11-1 1111
xxxx xxxx uuuu uuuu
PSPIP
OSCFIF
OSCFIE
OSCFIP
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
—
—
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
ADCON0
ADCON1
ADCON2
PORTA
TRISA
—
—
—
—
CHS3
VCFG1
ACQT2
RA5
CHS3
VCFG0
ACQT1
RA4
CHS1
CHS0 GO/DONE ADON
--00 0000 --00 0000
PCFG0 --00 qqqq --00 qqqq
ADCS0 0-00 0000 0-00 0000
PCFG3 PCFG2
ACQT0 ADCS2
PCFG1
ADCS1
RA1
ADFM
—
(4)
(4)
RA7
RA6
RA3
RA2
RA0
--0x 0000 --0u 0000
--11 1111 --11 1111
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
---- xxxx ---- uuuu
0000 -111 0000 -111
---- -xxx ---- -uuu
(4)
(4)
TRISA7
TRISA6
PORTB
TRISB
Read PORTB pins, Write LATB Latch
PORTB Data Direction Register
PORTB Output Data Latch
LATB
(2)
(4)
PORTE
—
IBF
—
—
OBE
—
—
IBOV
—
—
PSPMODE
—
RE3
—
Read PORTE pins, Write LATE
PORTE Data Direction
(3)
TRISE
(3)
LATE
PORTE Output Data Latch
Legend:
x= unknown, u= unchanged, - = unimplemented, read as ‘0’, q= value depends on condition.
Shaded cells are not used for A/D conversion.
Note 1: RE3 port bit is available only as an input pin when MCLRE bit in configuration register is ‘0’.
2: This register is not implemented on PIC18F2X20 devices.
3: These bits are not implemented on PIC18F2X20 devices.
4: These pins may be configured as port pins depending on the oscillator mode selected.
DS39599C-page 220
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
