PIC18F2220/2320/4220/4320
(PIE1<4>). Flag bit TXIF will be set regardless of the
18.4 USART Synchronous Master
Mode
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit, TRMT (TXSTA<1>),
shows the status of the TSR register. TRMT is a read-
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit so the user has to poll this bit
in order to determine if the TSR register is empty. The
TSR is not mapped in data memory so it is not available
to the user.
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit, SYNC (TXSTA<4>). In
addition, enable bit, SPEN (RCSTA<7>), is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit, CSRC (TXSTA<7>).
To set up a Synchronous Master Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 18.2 “USART Baud Rate
Generator (BRG)”).
18.4.1
USART SYNCHRONOUS MASTER
TRANSMISSION
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG is empty and inter-
rupt bit, TXIF (PIR1<4>), is set. The interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 18-6:
SYNCHRONOUS TRANSMISSION
Q1 Q2 Q3Q4 Q1 Q2Q3 Q4 Q1 Q2Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3 Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
RC7/RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
RC6/TX/CK
pin
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT
TRMT bit
‘1’
‘1’
TXEN bit
Note: Sync Master mode, SPBRG = 0; continuous transmission of two 8-bit words.
DS39599C-page 206
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
