PIC18F2220/2320/4220/4320
The primary clock source may never become ready dur-
ing start-up. In this case, operation is clocked by the
INTOSC multiplexer. The OSCCON register will remain in
its Reset state until a power managed mode is entered.
23.4.2
EXITING FAIL-SAFE OPERATION
The fail-safe condition is terminated by either a device
Reset or by entering a power managed mode. On Reset,
the controller starts the primary clock source specified in
Configuration Register 1H (with any required start-up
delays that are required for the oscillator mode, such as
OST or PLL timer). The INTOSC multiplexer provides the
system clock until the primary clock source becomes
ready (similar to a Two-speed Start-up). The clock system
source is then switched to the primary clock (indicated by
the OSTS bit in the OSCCON register becoming set). The
Fail-Safe Clock Monitor then resumes monitoring the
peripheral clock.
Entering a power managed mode by loading the
OSCCON register and executing a SLEEP instruction
will clear the fail-safe condition. When the fail-safe
condition is cleared, the clock monitor will resume
monitoring the peripheral clock.
FIGURE 23-4:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
CM Output
(Q)
Failure
Detected
OSCFIF
CM Test
CM Test
CM Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
2003 Microchip Technology Inc.
DS39599C-page 249
MICROCHIP [ MICROCHIP ]
