PIC18F2220/2320/4220/4320
Each of the five blocks has three code protection bits
associated with them. They are:
23.5 Program Verification and
Code Protection
• Code-Protect bit (CPn)
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro® devices.
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 23-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code protec-
tion bit associated with each block. The actual locations
of the bits are summarized in Table 23-3.
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into four blocks on binary
boundaries.
FIGURE 23-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2X20/4X20
MEMORY SIZE/DEVICE
Block Code Protection
4 Kbytes
(PIC18F2220/4220)
8 Kbytes
(PIC18F2320/4320)
Address
Range
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000000h
0001FFh
Boot Block
Boot Block
Block 0
000200h
Block 0
Block 1
0007FFh
000800h
Block 1
Block 2
Block 3
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
000FFFh
001000h
Unimplemented
Read ‘0’s
0017FFh
001800h
Unimplemented
Read ‘0’s
001FFFh
002000h
Unimplemented
Unimplemented
Read ‘0’s
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
300008h
300009h
CONFIG5L
CONFIG5H
—
CPD
—
—
CPB
—
—
—
—
—
—
—
—
—
CP3
—
CP2
—
CP1
—
CP0
—
30000Ah CONFIG6L
—
WRT3
—
WRT2
—
WRT1
—
WRT0
—
30000Bh CONFIG6H WRTD
WRTB
—
WRTC
—
30000Ch CONFIG7L
30000Dh CONFIG7H
—
—
EBTR3
—
EBTR2
—
EBTR1
—
EBTR0
—
EBTRB
—
Legend: Shaded cells are unimplemented.
2003 Microchip Technology Inc.
DS39599C-page 251
MICROCHIP [ MICROCHIP ]
