PIC18F2220/2320/4220/4320
Since the postscaler frequency from the internal oscil-
23.4 Fail-Safe Clock Monitor
lator block may not be sufficiently stable, it may be
desirable to select another clock configuration and
enter an alternate power managed mode (see
Section 23.3.1 “Special Considerations for Using
Two-Speed Start-up” and Section 3.1.3 “Multiple
Sleep Commands” for more details). This can be
done to attempt a partial recovery or execute a
controlled shutdown.
The Fail-Safe Clock Monitor (FSCM) allows the micro-
controller to continue operation, in the event of an
external oscillator failure, by automatically switching
the system clock to the internal oscillator block. The
FSCM function is enabled by setting the Fail-Safe
Clock Monitor Enable bit, FCMEN (CONFIG1H<6>).
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide
an instant backup clock in the event of a clock failure.
Clock monitoring (shown in Figure 23-3) is accom-
plished by creating a sample clock signal, which is the
INTRC output divided by 64. This allows ample time
between FSCM sample clocks for a peripheral clock
edge to occur. The peripheral system clock and the
sample clock are presented as inputs to the Clock Mon-
itor latch (CM). The CM is set on the falling edge of the
system clock source but cleared on the rising edge of
the sample clock.
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits IFRC2:IFRC0
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting IFRC2:IFRC0 prior to entering Sleep mode.
Adjustments to the internal oscillator block using the
OSCTUNE register also affect the period of the FSCM
by the same factor. This can usually be neglected, as
the clock frequency being monitored is generally much
higher than the sample clock frequency.
The FSCM will detect failures of the primary or second-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
FIGURE 23-3:
FSCM BLOCK DIAGRAM
Clock Monitor
Latch (CM)
(edge-triggered)
Peripheral
Clock
S
Q
23.4.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a sep-
arate divider and counter, disabling the WDT has no
effect on the operation of the INTRC oscillator when the
FSCM is enabled.
INTRC
Source
C
Q
÷ 64
(32 µs)
488 Hz
(2.048 ms)
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF2:IRCF0 bits, this may mean a substantial change
in the speed of code execution. If the WDT is enabled
with a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, fail-safe clock events
also reset the WDT and postscaler, allowing it to start
timing from when execution speed was changed and
decreasing the likelihood of an erroneous time-out.
Clock
Failure
Detected
Clock failure is tested on the falling edge of the sample
clock. If a sample clock falling edge occurs while CM is
still set, a clock failure has been detected (Figure 23-4).
This causes the following:
• The FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>)
• The system clock source is switched to the
internal oscillator block (OSCCON is not updated
to show the current clock source – this is the
fail-safe condition)
• The WDT is reset
DS39599C-page 248
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
