PIC18F2220/2320/4220/4320
FIGURE 21-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
16 Stages
CVREN
R
R
R
R
8R
CVRR
RA2/AN2/VREF-/CVREF
8R
CVROE
CVR3
(From CVRCON<3:0>)
CVR0
CVREF
16-1 Analog Mux
21.2 Voltage Reference Accuracy/Error
21.4 Effects of a Reset
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 21-1) keep CVREF from approaching the refer-
ence source rails. The voltage reference is derived
from VDD; therefore, the CVREF output changes with
fluctuations in VDD. The tested absolute accuracy of
the voltage reference can be found in Section 26.0
“Electrical Characteristics”.
A device Reset disables the voltage reference by clear-
ing the CVRCON register. This also disconnects the
reference from the RA2 pin, selects the high-voltage
range and selects the lowest voltage tap from the
resistor divider.
21.5 Connection Considerations
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be output using the RA2 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto the RA2 pin, with an input signal present, will
increase current consumption.
21.3 Operation in Power Managed
Modes
The contents of the CVRCON register are not affected
by entry to or exit from power managed modes. To min-
imize current consumption in power managed modes,
the voltage reference module should be disabled; how-
ever, this can cause an interrupt from the comparators
so the comparator interrupt should also be disabled
while the CVRCON register is being modified.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, an external buffer must be used on the
voltage reference output for external connections to
VREF. Figure 21-2 shows an example buffering
technique.
DS39599C-page 228
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
