欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F2320-I/SP的Datasheet PDF文件第8页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第9页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第10页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第11页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第13页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第14页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第15页浏览型号PIC18F2320-I/SP的Datasheet PDF文件第16页  
PIC18F2220/2320/4220/4320  
FIGURE 1-2:  
PIC18F4220/4320 BLOCK DIAGRAM  
Data Bus<8>  
PORTA  
Data Latch  
Data RAM  
RA0/AN0  
RA1/AN1  
RA2/AN2/VREF-/CVREF  
RA3/AN3/VREF+  
Table Pointer <2>  
inc/dec logic  
21  
8
8
8
8
(512 Bytes)  
21  
RA4/T0CKI/C1OUT  
RA5/AN4/SS/LVDIN/C2OUT  
OSC2/CLKO/RA6(3)  
OSC1/CLKI/RA7(3)  
21  
Address Latch  
20  
PCLATU PCLATH  
12(2)  
Address Latch  
Program Memory  
(8 Kbytes)  
Address<12>  
PCU PCH PCL  
Program Counter  
4
BSR  
12  
FSR0  
4
PORTB  
Data Latch  
Bank0, F  
RB0/AN12/INT0  
RB1/AN10/INT1  
RB2/AN8/INT2  
RB3/AN9/CCP2(1)  
RB4/AN11/KBI0  
RB5/KBI1/PGM  
RB6/KBI2/PGC  
RB7/KBI3/PGD  
FSR1  
FSR2  
31 Level Stack  
12  
16  
inc/dec  
logic  
Decode  
Table Latch  
8
ROM Latch  
PORTC  
RC0/T1OSO/T1CKI  
RC1/T1OSI/CCP2(1)  
RC2/CCP1/P1A  
RC3/SCK/SCL  
RC4/SDI/SDA  
RC5/SDO  
Instruction  
Register  
8
Instruction  
Decode &  
Control  
RC6/TX/CK  
RC7/RX/DT  
PRODH PRODL  
8 x 8 Multiply  
3
PORTD  
8
RD0/PSP0  
RD1/PSP1  
RD2/PSP2  
RD3/PSP3  
RD4/PSP4  
RD5/PSP5/P1B  
RD6/PSP6/P1C  
RD7/PSP7/P1D  
BIT OP  
8
WREG  
8
OSC1(3)  
OSC2(3)  
T1OSI  
Internal  
Oscillator  
Block  
Power-up  
Timer  
8
Oscillator  
Start-up Timer  
8
INT RC  
Oscillator  
ALU<8>  
Power-on  
Reset  
T1OSO  
8
Watchdog  
Timer  
PORTE  
Precision  
Voltage  
Reference  
RE0/AN5/RD  
Brown-out  
Reset  
Low-Voltage  
Programming  
RE1/AN6/WR  
RE2/AN7/CS  
RE3(2)  
(2)  
MCLR  
Fail-Safe  
Clock Monitor  
In-Circuit  
Debugger  
VDD, VSS  
Timer1  
(16-bit)  
Timer2  
(8-bit)  
Timer3  
(16-bit)  
10-bit A/D  
Converter  
Timer0  
(8- or 16-bit)  
Master  
Synchronous  
Serial Port  
Addressable  
USART  
Data EEPROM  
(256 Bytes)  
Enhanced  
CCP  
CCP2  
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCP2MX configuration bit.  
2: RE3 is available only when the MCLR Resets are disabled.  
3: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.  
Refer to Section 2.0 “Oscillator Configurations” for additional information.  
DS39599C-page 10  
2003 Microchip Technology Inc.