PIC17C4X
Steps to follow when setting up an Asynchronous
Reception:
7. Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred dur-
ing reception.
1. Initialize the SPBRG register for the appropriate
baud rate.
8. Read RCREG for the 8-bit received data.
9. If an overrun error occurred, clear the error by
clearing the OERR bit.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are desired, then set the RCIE bit.
4. If 9-bit reception is desired, then set the RX9 bit.
5. Enable the reception by setting the CREN bit.
Note: To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
6. The RCIF bit will be set when reception com-
pletes and an interrupt will be generated if the
RCIE bit was set.
FIGURE 13-8: ASYNCHRONOUS RECEPTION
Start
RX
Start
bit
Start
bit
bit
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
(RA4/RX/DT pin)
Rcv shift
reg
Rcv buffer reg
Word 3
Word 2
RCREG
Word 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 13-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 1
13h, Bank 0
14h, Bank 0
17h, Bank 1
15h, Bank 0
17h, Bank 0
PIR
RBIF
SPEN
RX7
TMR3IF TMR2IF TMR1IF CA2IF
CA1IF
FERR
RX2
TXIF
OERR
RX1
RCIF
RX9D
RX0
0000 0010
0000 -00x
xxxx xxxx
0000 0000
0000 --1x
xxxx xxxx
0000 0010
0000 -00u
uuuu uuuu
0000 0000
0000 --1u
uuuu uuuu
RCSTA
RCREG
PIE
RX9
RX6
SREN
RX5
CREN
RX4
—
RX3
RBIE
CSRC
TMR3IE TMR2IE TMR1IE CA2IE
TX9 TXEN SYNC
CA1IE
—
TXIE
RCIE
TX9D
TXSTA
SPBRG
—
TRMT
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for asynchronous reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 92
1996 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
