PIC17C4X
FIGURE 13-5: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
TX
Start Bit
Bit 0
Bit 1
Word 1
Bit 7/8
(RA5/TX/CK pin)
Stop Bit
TXIF bit
Word 1
Transmit Shift Reg
TRMT bit
FIGURE 13-6: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
TX
Start Bit
Start Bit
Word 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Stop Bit
(RA5/TX/CK pin)
Word 1
TXIF bit
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
Note: This timing diagram shows two consecutive transmissions.
TABLE 13-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
Power-on
Reset
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
16h, Bank 1
13h, Bank 0
16h, Bank 0
17h, Bank 1
15h, Bank 0
17h, Bank 0
PIR
RBIF
TMR3IF TMR2IF TMR1IF CA2IF CA1IF
RX9 SREN CREN FERR
TXIF
RCIF
0000 0010
0000 -00x
xxxx xxxx
0000 0000
0000 --1x
xxxx xxxx
0000 0010
0000 -00u
uuuu uuuu
0000 0000
0000 --1u
uuuu uuuu
RCSTA
TXREG
PIE
SPEN
—
OERR
RX9D
Serial port transmit register
RBIE
TMR3IE TMR2IE TMR1IE CA2IE CA1IE
TX9 TXEN SYNC
TXIE
RCIE
TX9D
TXSTA
SPBRG
CSRC
—
—
TRMT
Baud rate generator register
Legend: x= unknown, u= unchanged, -= unimplemented read as a '0', shaded cells are not used for asynchronous
transmission.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
DS30412C-page 90
1996 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
