PIC17C4X
7.2.2
TABLE WRITE CODE
7.2
Table Writes to External Memory
The “i” operand of the TABLWTinstruction can specify
that the value in the 16-bit TBLPTR register is auto-
matically incremented for the next write. In
Example 7-1, the TBLPTR register is not automatically
incremented.
Table writes to external memory are always two-cycle
instructions. The second cycle writes the data to the
external memory location. The sequence of events for
an external memory write are the same for an internal
write.
EXAMPLE 7-1: TABLE WRITE
Note: If an interrupt is pending or occurs during
the TABLWT, the two cycle table write
completes. The RA0/INT, TMR0, or T0CKI
interrupt flag is automatically cleared or
the pending peripheral interrupt is
acknowledged.
CLRWDT
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
TLWT
; Clear WDT
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
HIGH (DATA)
1, WREG
;
;
;
address
; Load HI byte
in TABLATCH
; Load LO byte
;
MOVLW
LOW (DATA)
TABLWT 0,0,WREG
;
;
;
;
in TABLATCH
and write to
program memory
(Ext. SRAM)
FIGURE 7-5: TABLWT WRITE TIMING (EXTERNAL MEMORY)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
PC
PC+1
TBL
Data out
PC+2
Instruction
fetched
TABLWT
INST (PC+1)
INST (PC+2)
INST (PC+1)
Instruction
executed
INST (PC-1)
TABLWT cycle1
TABLWT cycle2
Data write cycle
ALE
OE
'1'
WR
Note: If external write GLINTD = '1', Enable bit = '1', '1' → Flag bit, Do table write. The highest pending interrupt is cleared.
DS30412C-page 46
1996 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
