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PIC17LC42-16I/JW 参数 Datasheet PDF下载

PIC17LC42-16I/JW图片预览
型号: PIC17LC42-16I/JW
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位CMOS EPROM / ROM微控制器 [High-Performance 8-Bit CMOS EPROM/ROM Microcontroller]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 240 页 / 1141 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC17C4X  
For the PIC17C43, PIC17CR43, and PIC17C44  
devices, the need for a large general purpose memory  
space dictated a general purpose RAM banking  
scheme. The upper nibble of the BSR selects the cur-  
rently active general purpose RAM bank. To assist this,  
a MOVLR bank instruction has been provided in the  
instruction set.  
6.8  
Bank Select Register (BSR)  
The BSR is used to switch between banks in the data  
memory area (Figure 6-13). In the PIC17C42,  
PIC17CR42, and PIC17C42A only the lower nibble is  
implemented. While in the PIC17C43, PIC17CR43,  
and PIC17C44 devices, the entire byte is implemented.  
The lower nibble is used to select the peripheral regis-  
ter bank. The upper nibble is used to select the general  
purpose memory bank.  
If the currently selected bank is not implemented (such  
as Bank 13), any read will read all '0's. Any write is com-  
pleted to the bit bucket and the ALU status bits will be  
set/cleared as appropriate.  
All the Special Function Registers (SFRs) are mapped  
into the data memory space. In order to accommodate  
the large number of registers, a banking scheme has  
been used. A segment of the SFRs, from address 10h  
to address 17h, is banked.The lower nibble of the bank  
select register (BSR) selects the currently active  
“peripheral bank.Effort has been made to group the  
peripheral registers of related functionality in one bank.  
However, it will still be necessary to switch from bank  
to bank in order to address all peripherals related to a  
single task. To assist this, a MOVLB bankinstruction is  
in the instruction set.  
Note: Registers in Bank 15 in the Special Func-  
tion Register area, are reserved for  
Microchip use. Reading of registers in this  
bank may cause random values to be read.  
FIGURE 6-13: BSR OPERATION (PIC17C43/R43/44)  
BSR  
7
4 3  
0
(2)  
(1)  
Address  
Range  
0
1
2
3
4
15  
SFR  
Banks  
10h  
17h  
• • •  
Bank 0  
0
Bank 1  
1
Bank 2  
2
Bank 3  
Bank 4  
Bank 15  
15  
20h  
FFh  
GPR  
Banks  
• • •  
• • •  
Bank 0  
Bank 1  
Bank 2  
Bank 15  
Note 1: Only Banks 0 through Bank 3 are implemented. Selection of an unimplemented bank is not recommended.  
Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.  
2: Only Banks 0 and Bank 1 are implemented. Selection of an unimplemented bank is not recommended.  
DS30412C-page 42  
1996 Microchip Technology Inc.  
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