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PIC17LC42-16I/JW 参数 Datasheet PDF下载

PIC17LC42-16I/JW图片预览
型号: PIC17LC42-16I/JW
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位CMOS EPROM / ROM微控制器 [High-Performance 8-Bit CMOS EPROM/ROM Microcontroller]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 240 页 / 1141 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第44页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第45页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第46页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第47页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第49页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第50页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第51页浏览型号PIC17LC42-16I/JW的Datasheet PDF文件第52页  
PIC17C4X  
7.3  
Table Reads  
EXAMPLE 7-2: TABLE READ  
MOVLW  
MOVWF  
MOVLW  
MOVWF  
TABLRD 0,0,DUMMY  
TLRD 1, INDF0  
TABLRD 0,1,INDF0  
HIGH (TBL_ADDR) ; Load the Table  
The table read allows the program memory to be read.  
This allows constant data to be stored in the program  
memory space, and retrieved into data memory when  
needed. Example 7-2 reads the 16-bit value at pro-  
gram memory address TBLPTR. After the dummy byte  
has been read from the TABLATH, the TABLATH is  
loaded with the 16-bit data from program memory  
address TBLPTR + 1. The first read loads the data into  
the latch, and can be considered a dummy read  
(unknown data loaded into 'f'). INDF0 should be con-  
figured for either auto-increment or auto-decrement.  
TBLPTRH  
LOW (TBL_ADDR)  
TBLPTRL  
;
;
;
address  
; Dummy read,  
Updates TABLATCH  
; Read HI byte  
of TABLATCH  
; Read LO byte  
;
;
;
;
of TABLATCH and  
Update TABLATCH  
FIGURE 7-7: TABLRD TIMING  
Q4  
Q4  
Q4  
Q1 Q2  
Q3  
Q4  
Q1 Q2  
Q1 Q2  
Q1 Q2  
Q3  
Q3  
Q3  
AD15:AD0  
PC  
PC+1  
TBL  
Data in  
PC+2  
Instruction  
fetched  
INST (PC+2)  
TABLRD  
INST (PC+1)  
Instruction  
executed  
INST (PC-1)  
TABLRD cycle2  
Data read cycle  
INST (PC+1)  
TABLRD cycle1  
ALE  
OE  
'1'  
WR  
FIGURE 7-8: TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
Data in 1  
PC  
TBL1  
PC+2  
TBL2 Data in 2  
AD15:AD0  
PC+1  
PC+3  
Instruction  
fetched  
TABLRD1  
INST (PC+2)  
INST (PC+3)  
INST (PC+2)  
TABLRD2  
Instruction  
executed  
INST (PC-1) TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1  
Data read cycle  
TABLRD2 cycle2  
Data read cycle  
ALE  
OE  
'1'  
WR  
DS30412C-page 48  
1996 Microchip Technology Inc.  
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