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PIC17LC42-16I/JW 参数 Datasheet PDF下载

PIC17LC42-16I/JW图片预览
型号: PIC17LC42-16I/JW
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位CMOS EPROM / ROM微控制器 [High-Performance 8-Bit CMOS EPROM/ROM Microcontroller]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 240 页 / 1141 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC17C4X  
IORWF  
Inclusive OR WREG with f  
[ label ] IORWF f,d  
0 f 255  
LCALL  
Long Call  
Syntax:  
Syntax:  
[ label ] LCALL  
0 k 255  
k
Operands:  
Operands:  
Operation:  
d
[0,1]  
PC + 1 TOS;  
Operation:  
(WREG) .OR. (f) (dest)  
k PCL, (PCLATH) PCH  
Status Affected:  
Encoding:  
Z
Status Affected:  
Encoding:  
None  
0000  
100d  
ffff  
ffff  
1011  
0111  
kkkk  
kkkk  
Inclusive OR WREG with register 'f'. If  
'd' is 0 the result is placed in WREG. If  
'd' is 1 the result is placed back in regis-  
ter 'f'.  
LCALLallows an unconditional subrou-  
tine call to anywhere within the 64k pro-  
gram memory space.  
Description:  
Description:  
First, the return address (PC + 1) is  
pushed onto the stack. A 16-bit desti-  
nation address is then loaded into the  
program counter. The lower 8-bits of  
the destination address is embedded in  
the instruction. The upper 8-bits of PC  
is loaded from PC high holding latch,  
PCLATH.  
Words:  
Cycles:  
1
1
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Decode  
Read  
Execute  
Write to  
register 'f'  
destination  
Words:  
Cycles:  
1
2
IORWF RESULT, 0  
Example:  
Before Instruction  
Q Cycle Activity:  
Q1  
RESULT =  
0x13  
0x91  
Q2  
Q3  
Q4  
WREG  
=
Decode  
Read  
literal 'k'  
Execute  
Write  
register PCL  
After Instruction  
RESULT =  
0x13  
0x93  
Forced NOP  
Example:  
NOP  
Execute  
NOP  
WREG  
=
MOVLW HIGH(SUBROUTINE)  
MOVPF WREG, PCLATH  
LCALL LOW(SUBROUTINE)  
Before Instruction  
SUBROUTINE =  
16-bit Address  
?
PC  
=
After Instruction  
PC  
=
Address (SUBROUTINE)  
1996 Microchip Technology Inc.  
DS30412C-page 125  
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