PIC17C75X
FIGURE 10-12: BLOCK DIAGRAM OF RE3/CAP4 PORT PIN
Peripheral In
Data Bus
D
Q
EN
EN
VDD
RD_PORTE
WR_PORTE
P
Q
D
D
Port
Data
CK
Q
N
RD_DDRE
WR_DDRE
Q
CK
S
Q
Note: I/O pin has protection diodes to VDD and Vss.
TABLE 10-9: PORTE FUNCTIONS
Name
Bit
Buffer Type
Function
RE0/ALE
RE1/OE
bit0
bit1
bit2
bit3
TTL
TTL
TTL
ST
Input/Output or system bus Address Latch Enable (ALE) control pin.
Input/Output or system bus Output Enable (OE) control pin.
Input/Output or system bus Write (WR) control pin.
Input/Output or Capture4 input pin
RE2/WR
RE3/CAP4
Legend: TTL = TTL input.
ST = Schmitt Trigger input
TABLE 10-10: REGISTERS/BITS ASSOCIATED WITH PORTE
Value on,
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15h, Bank 1 PORTE
14h, Bank 1 DDRE
—
—
—
—
RE3/CAP4 RE2/WR RE1/OE RE0/ALE ---- xxxx
---- uuuu
---- 1111
Data direction register for PORTE
Capture4 low byte
---- 1111
14h, Bank 7 CA4L
15h, Bank 7 CA4H
16h, Bank 7 TCON3
xxxx xxxx
xxxx xxxx
uuuu uuuu
uuuu uuuu
-000 0000
Capture4 high byte
—
CA4OVF CA3OVF CA4ED1 CA4ED0
CA3ED1 CA3ED0 PWM3ON -000 0000
Legend: x= unknown, u= unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 77
MICROCHIP [ MICROCHIP ]
