PIC17C75X
TABLE 7-3:
SPECIAL FUNCTION REGISTERS (Cont.’d)
Value on
POR,
BOR
Value on
all other
resets (3)
Address Name
Bank 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10h
11h
12h
13h
14h
15h
16h
17h
TMR1
Timer1’s register
Timer2’s register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR2
TMR3L
TMR3H
PR1
Timer3’s register; low byte
Timer3’s register; high byte
Timer1’s period register
Timer2’s period register
PR2
PR3L/CA1L
PR3H/CA1H
Timer3’s period register - low byte/capture1 register; low byte
Timer3’s period register - high byte/capture1 register; high byte
Bank 3
10h
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
DC1
DC1
DC9
DC9
DC0
DC0
DC8
DC8
—
TM2PW2
DC7
—
—
—
—
—
—
—
—
—
—
xx-- ---- uu-- ----
xx0- ---- uu0- ----
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
11h
12h
DC6
DC6
DC5
DC5
DC4
DC4
DC3
DC3
DC2
DC2
13h
DC7
14h
Capture2 low byte
Capture2 high byte
15h
CA2H
16h
TCON1
CA2ED1 CA2ED0 CA1ED1
CA1ED0
T16
TMR3CS
TMR2CS TMR1CS 0000 0000 0000 0000
17h
TCON2
CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
Bank 4:
10h
PIR2
SSPIF
SSPIE
—
BCLIF
BCLIE
—
ADIF
ADIE
—
—
—
CA4IF
CA4IE
—
CA3IF
CA3IE
—
TX2IF
TX2IE
—
RC2IF
RC2IE
—
000- 0010 000- 0010
000- 0000 000- 0000
---- ---- ---- ----
0000 -00x 0000 -00u
xxxx xxxx uuuu uuuu
0000 --1x 0000 --1u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
11h
PIE2
12h
Unimplemented
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
—
13h
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
14h
Serial Port Receive Register for USART2
CSRC TX9 TXEN SYNC
15h
—
—
TRMT
TX9D
16h
Serial Port Transmit Register for USART2
Baud Rate Generator for USART2
17h
Bank 5:
10h
DDRF
Data Direction Register for PORTF
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
xxxx 0000 uuuu 0000
0000 -0-0 0000 -0-0
11h
PORTF
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
12h
13h
DDRG
Data Direction Register for PORTG
PORTG
RG7/
RG6/
RG5/
RG4/
CAP3
RG3/
AN0
RG2/
AN1
RG1/
AN2
RG0/
AN3
TX2/CK2 RX2/DT2
PWM3
14h
15h
16h
17h
ADCON0
ADCON1
ADRESL
ADRESH
CHS3
CHS2
CHS1
ADFM
CHS0
—
—
GO/DONE
PCFG2
—
ADON
ADCS1
ADCS0
PCFG3
PCFG1
PCFG0 000- 0000 000- 0000
xxxx xxxx uuuu uuuu
A/D Result Register low byte
A/D Result Register high byte
xxxx xxxx uuuu uuuu
Legend:
Note 1:
x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated
from or transferred to the upper byte of the program counter.
2: The TO and PD status bits in CPUSTA are not affected by a MCLR reset.
3: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 45
MICROCHIP [ MICROCHIP ]
