PIC17C75X
FIGURE 7-5: PIC17C75X REGISTER FILE MAP
Addr Unbanked
INDF0
FSR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
PCL
PCLATH
ALUSTA
T0STA
CPUSTA
INTSTA
INDF1
FSR1
WREG
TMR0L
TMR0H
TBLPTRL
TBLPTRH
BSR
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
Bank 6
Bank 7
PORTA
DDRB
DDRC
TMR1
TMR2
PW1DCL
PW2DCL
PW1DCH
PW2DCH
CA2L
PIR2
PIE2
—
DDRF
SSPADD
SSPCON1
SSPCON2
SSPSTAT
SSPBUF
—
PW3DCL
PW3DCH
CA3L
10h
11h
12h
13h
14h
15h
16h
17h
PORTC
DDRD
PORTD
DDRE
PORTE
PIR1
PORTF
DDRG
PORTB
TMR3L
TMR3H
PR1
RCSTA1
RCREG1
TXSTA1
TXREG1
SPBRG1
Unbanked
RCSTA2
RCREG2
TXSTA2
TXREG2
SPBRG2
PORTG
ADCON0
ADCON1
ADRESL
ADRESH
CA3H
CA4L
PR2
CA2H
CA4H
TCON3
—
—
PR3L/CA1L
PR3H/CA1H
TCON1
TCON2
—
PIE1
PRODL
PRODH
18h
19h
1Ah
General
Purpose
RAM
1Fh
20h
(2)
(2)
(2, 3)
(2, 3)
Bank 0
Bank 1
Bank 2
Bank 3
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
FFh
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All
unbanked SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh
are banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select
Register (BSR) bits.
3: These RAM banks are not implemented on the PIC17C752. Reading any register in this bank reads
‘0’s
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 43
MICROCHIP [ MICROCHIP ]
