PIC17C75X
FIGURE 14-3: USART TRANSMIT
Sync
Master/Slave
BRG
÷ 4
Sync/Async
CK/TX
Sync/Async
Sync/Async
TSR
÷ 16
Clock
• • •
Start 0 1
7 8 Stop
DT
Load
Bit Count
TXEN/
Write to TXREG
8
• • •
0 1
7
TXREG
Interrupt
TXSTA<0>
Data Bus
TXIE
FIGURE 14-4: USART RECEIVE
Interrupt
RCIE
OSC
÷ 4
BRG
Master/Slave
Sync
Sync/Async
Async/Sync
enable
Buffer
Logic
Bit Count
÷ 16
CK
RX
START
Detect
SPEN
SREN/
CREN/
Start_Bit
RSR
Majority
Detect
Buffer
Logic
Clock
Data
MSb
Stop 8 7
LSb
1 0
• • •
FIFO
Logic
RX9
Async/Sync
RCREG
Clk
FIFO
• • •
• • •
RX9D
RX9D
7
7
1 0
1 0
FERR
FERR
Data Bus
1997 Microchip Technology Inc.
Preliminary
DS30264A-page 109