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PIC16F916-I/SO 参数 Datasheet PDF下载

PIC16F916-I/SO图片预览
型号: PIC16F916-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28 / 44/ 64引脚基于闪存的8位CMOS微控制器与LCD驱动器和纳瓦技术 [28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology]
分类和应用: 驱动器闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 330 页 / 6045 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F913/914/916/917/946  
11.1 PLVD Operation  
11.4 Stable Reference Indication  
To setup the PLVD for operation, the following steps  
must be taken:  
When the PLVD module is enabled, the reference volt-  
age must be allowed to stabilize before the PLVD will  
provide a valid result. Refer to Section 19.0 “Electri-  
cal Specifications”, Table 19-13, for the stabilization  
time.  
• Enable the module by setting the LVDEN bit of the  
LVDCON register.  
• Configure the trip point by setting the LVDL<2:0>  
bits of the LVDCON register.  
When the HFINTOSC is running, the IRVST bit of the  
LVDCON register indicates the stability of the voltage  
reference. The voltage reference is stable when the  
IRVST bit is set.  
• Wait for the reference voltage to become stable.  
Refer to Section 11.4 “Stable Reference  
Indication”.  
• Clear the LVDIF bit of the PIR2 register.  
11.5 Operation During Sleep  
The LVDIF bit will be set when VDD falls below the  
PLVD trip point. The LVDIF bit remains set until cleared  
by software. Refer to Figure 11-2.  
To wake from Sleep, set the LVDIE bit of the PIE2  
register and the PEIE bit of the INTCON register. When  
the LVDIE and PEIE bits are set, the device will wake  
from Sleep and execute the next instruction. If the GIE  
bit is also set, the program will call the Interrupt Service  
Routine upon completion of the first instruction after  
waking from Sleep.  
11.2 Programmable Trip Point  
The PLVD trip point is selectable from one of eight  
voltage levels. The LVDL bits of the LVDCON register  
select the trip point. Refer to Register 11-1 for the  
available PLVD trip points.  
11.3 Interrupt on Falling VDD  
When VDD falls below the PLVD trip point, the falling  
edge detector will set the LVDIF bit. See Figure 11-2.  
An interrupt will be generated if the following bits are  
also set:  
• GIE and PEIE bits of the INTCON register  
• LVDIE bit of the PIE2 register  
The LVDIF bit must be cleared by software. An interrupt  
can be generated from a simulated PLVD event when  
the LVDIF bit is set by software.  
DS41250F-page 172  
© 2007 Microchip Technology Inc.  
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