PIC16F87/88
9.2.1
CCP PIN CONFIGURATION
9.2
Compare Mode
The user must configure the CCP1 pin as an output by
clearing the TRISB<x> bit.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
Note 1: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the data
latch.
• Driven high
• Driven low
• Remains unchanged
2: The TRISB bit (0 or 3) is dependent upon
the setting of configuration bit 12
(CCPMX).
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit, CCP1IF, is set.
9.2.2
TIMER1 MODE SELECTION
FIGURE 9-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
9.2.3
SOFTWARE INTERRUPT MODE
CCPR1H CCPR1L
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
Q
S
R
Output
Logic
Comparator
Match
CCP1 pin
TRISB<x>
9.2.4
SPECIAL EVENT TRIGGER
TMR1H TMR1L
Output Enable
CCP1CON<3:0>
Mode Select
In this mode, an internal hardware trigger is generated
that may be used to initiate an action.
Special event trigger will:
•
RESET Timer1, but not set interrupt flag bit, TMR1IF
(PIR1<0>)
Set bit GO/DONE (ADCON0<2>) bit, which starts an A/D
conversion
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1 regis-
ter to effectively be a 16-bit programmable period
register for Timer1.
•
Note:
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TABLE 9-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Value on
all other
RESETS
Value on
POR, BOR
Address
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
INTCON
GIE
PEIE TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
10BH,18Bh
0Ch
8Ch
86h
0Eh
0Fh
10h
15h
16h
17h
PIR1
—
—
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
1111 1111 1111 1111
PIE1
TRISB
TMR1L
TMR1H
T1CON
CCPR1L
PORTB Data Direction Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register 1 (MSB)
CCP1CON CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
—
—
Legend: x= unknown, u= unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 83
MICROCHIP [ MICROCHIP ]
