PIC16F87/88
9.3.1
PWM PERIOD
9.3
PWM Mode
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula.
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<x> bit must be cleared to make the CCP1
pin an output.
EQUATION 9-1:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
PWM frequency is defined as 1/[PWM period].
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
For a step-by-step procedure on how to setup the CCP
module for PWM operation, see Section 9.3.3 “Setup
for PWM Operation”.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 9-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
Note: The Timer2 postscaler (see Section 8.0
“Timer2 Module”) is not used in the deter-
mination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Duty Cycle Registers
CCPR1L
CCPR1H (Slave)
Comparator
CCP1 pin
9.3.2
PWM DUTY CYCLE
Q
R
S
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time.
(Note 1)
TMR2
TRISB<x>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
EQUATION 9-2:
Note 1: 8-bit timer is concatenated with 2-bit internal Q
clock or 2 bits of the prescaler to create 10-bit
time base.
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
FIGURE 9-4:
PWM OUTPUT
The CCPR1H register and a 2-bit internal latch
are used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
Period
When the CCPR1H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP1 pin is cleared.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS30487B-page 84
Preliminary
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
