PIC16F882/883/884/886/887
REGISTER 8-5:
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
VREN
R/W-0
VROE
R/W-0
VRR
R/W-0
VRSS
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
VREN: Comparator C1 Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
VROE: Comparator C2 Voltage Reference Enable bit
1= CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2IN+ pin
0= CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2IN+ pin
VRR: CVREF Range Selection bit
1= Low range
0= High range
VRSS: Comparator VREF Range Selection bit
1= Comparator Reference Source, CVRSRC = (VREF+) - (VREF-)
0= Comparator Reference Source, CVRSRC = VDD - VSS
VR<3:0>: CVREF Value Selection 0 ≤ VR<3:0> ≤ 15
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
TABLE 8-3:
SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE
REFERENCE MODULES
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
ANSEL
ANS7
—
ANS6
—
ANS5
ANS13
C1OE
C2OE
ANS4
ANS12
C1POL
C2POL
ANS3
ANS11
—
ANS2
ANS10
C1R
C2R
—
ANS1
ANS9
ANS0
ANS8
1111 1111 1111 1111
--11 1111 --11 1111
0000 -000 0000 -000
0000 -000 0000 -000
ANSELH
CM1CON0
CM2CON0
C1ON
C2ON
C1OUT
C2OUT
C1CH1
C2CH1
C1CH0
C2CH0
—
CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL
—
T1GSS C2SYNC 0000 --10 0000 --10
INTCON
PIE2
GIE
OSFIE
OSFIF
RA7
PEIE
C2IE
C2IF
RA6
RB6
SR0
T0IE
C1IE
C1IF
INTE
EEIE
EEIF
RA4
RBIE
T0IF
INTF
—
RBIF
0000 000x 0000 000x
BCLIE ULPWUIE
BCLIF ULPWUIF
CCP2IE 0000 00-0 0000 00-0
CCP2IF 0000 00-0 0000 00-0
PIR2
—
PORTA
PORTB
SRCON
TRISA
TRISB
VRCON
Legend:
RA5
RA3
RB3
RA2
RB2
RA1
RB1
—
RA0
RB0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
RB7
RB5
RB4
SR1
C1SEN
C2SEN
PULSS
PULSR
TRISA2
TRISB2
VR2
FVREN 0000 00-0 0000 00-0
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3
TRISA1 TRISA0 1111 1111 1111 1111
TRISB1 TRISB0 1111 1111 1111 1111
VREN
VROE
VRR
VRSS
VR3
VR1
VR0
0000 0000 0000 0000
x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator.
© 2007 Microchip Technology Inc.
Preliminary
DS41291D-page 97
MICROCHIP [ MICROCHIP ]
