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PIC16F886-I/SS 参数 Datasheet PDF下载

PIC16F886-I/SS图片预览
型号: PIC16F886-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚,增强基于闪存的8位CMOS微控制器采用纳瓦技术 [28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 288 页 / 5120 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F882/883/884/886/887  
9.1.3  
ADC VOLTAGE REFERENCE  
9.1  
ADC Configuration  
The VCFG bits of the ADCON0 register provide  
independent control of the positive and negative  
voltage references. The positive voltage reference can  
be either VDD or an external voltage source. Likewise,  
the negative voltage reference can be either VSS or an  
external voltage source.  
When configuring and using the ADC the following  
functions must be considered:  
• Port configuration  
• Channel selection  
• ADC voltage reference selection  
• ADC conversion clock source  
• Interrupt control  
9.1.4  
CONVERSION CLOCK  
The source of the conversion clock is software select-  
able via the ADCS bits of the ADCON0 register. There  
are four possible clock options:  
• Results formatting  
9.1.1  
PORT CONFIGURATION  
• FOSC/2  
The ADC can be used to convert both analog and digital  
signals. When converting analog signals, the I/O pin  
should be configured for analog by setting the associated  
TRIS and ANSEL bits. See the corresponding Port  
section for more information.  
• FOSC/8  
• FOSC/32  
• FRC (dedicated internal oscillator)  
The time to complete one bit conversion is defined as  
TAD. One full 10-bit conversion requires 11 TAD periods  
as shown in Figure 9-3.  
Note:  
Analog voltages on any pin that is defined  
as a digital input may cause the input  
buffer to conduct excess current.  
For correct conversion, the appropriate TAD specification  
must be met. See A/D conversion requirements in  
Section 17.0 “Electrical Specifications” for more  
information. Table 9-1 gives examples of appropriate  
ADC clock selections.  
9.1.2  
CHANNEL SELECTION  
The CHS bits of the ADCON0 register determine which  
channel is connected to the sample and hold circuit.  
When changing channels, a delay is required before  
starting the next conversion. Refer to Section 9.2  
“ADC Operation” for more information.  
Note:  
Unless using the FRC, any changes in the  
system clock frequency will change the  
ADC clock frequency, which may  
adversely affect the ADC result.  
DS41291D-page 100  
Preliminary  
© 2007 Microchip Technology Inc.  
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