PIC16F882/883/884/886/887
8.10.3
OUTPUT CLAMPED TO VSS
8.10 Comparator Voltage Reference
The CVREF output voltage can be set to Vss with no
power consumption by configuring VRCON as follows:
The Comparator Voltage Reference module provides
an internally generated voltage reference for the com-
parators. The following features are available:
• VREN = 0
• VRR = 1
• Independent from Comparator operation
• Two 16-level voltage ranges
• Output clamped to VSS
• VR<3:0> = 0000
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module current.
• Ratiometric with VDD
• Fixed Reference (0.6V)
8.10.4
OUTPUT RATIOMETRIC TO VDD
The VRCON register (Register 8-5) controls the
Voltage Reference module shown in Figure 8-8.
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 17.0
“Electrical Specifications”.
The voltage source is selectable through both ends of
the 16 connection resistor ladder network. Bit VRSS of
the VRCON register selects either the internal or
external voltage source.
8.10.5
FIXED VOLTAGE REFERENCE
The PIC16F883/884/886/887 allows the CVREF signal
to be output to the RA2 pin of PORTA under certain
configurations only. For more details, see Figure 8-9.
The fixed voltage reference is independent of VDD, with
a nominal output voltage of 0.6V. This reference can be
enabled by setting the FVREN bit of the SRCON
register to ‘1’. This reference is always enabled when
the HFINTOSC oscillator is active.
8.10.1
INDEPENDENT OPERATION
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
8.10.6
FIXED VOLTAGE REFERENCE
STABILIZATION PERIOD
8.10.2
OUTPUT VOLTAGE SELECTION
When the fixed Voltage Reference module is enabled,
it will require some time for the reference and its
amplifier circuits to stabilize. The user program must
include a small delay routine to allow the module to
settle. See the electrical specifications section for the
minimum delay requirement.
The CVREF voltage reference has 2 ranges with 16
voltage levels in each range. Range selection is
controlled by the VRR bit of the VRCON register. The
16 levels are set with the VR<3:0> bits of the VRCON
register.
The CVREF output voltage is determined by the following
equations:
8.10.7
VOLTAGE REFERENCE
SELECTION
Multiplexers on the output of the Voltage Reference
module enable selection of either the CVREF or fixed
voltage reference for use by the comparators.
EQUATION 8-1:
CVREF OUTPUT VOLTAGE
VRR = 1 (low range):
CVREF = (VR<3:0>/24) × VLADDER
Setting the C1VREN bit of the VRCON register enables
current to flow in the CVREF voltage divider and selects
the CVREF voltage for use by C1. Clearing the C1VREN
bit selects the fixed voltage for use by C1.
VRR = 0 (high range):
CVREF = (VLADDER/4) + (VR<3:0> × VLADDER/32)
VLADDER = VDD or ([VREF+] - [VREF-]) or VREF+
Setting the C2VREN bit of the VRCON register enables
current to flow in the CVREF voltage divider and selects
the CVREF voltage for use by C2. Clearing the C2VREN
bit selects the fixed voltage for use by C2.
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 8-8.
When both the C1VREN and C2VREN bits are cleared,
current flow in the CVREF voltage divider is disabled
minimizing the power drain of the voltage reference
peripheral.
DS41291D-page 94
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
