PIC16F882/883/884/886/887
TABLE 2-3:
PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 2
100h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
37,213
73,213
37,213
29,213
37,213
101h TMR0
102h PCL
Program Counter’s (PC) Least Significant Byte
103h STATUS
104h FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
105h WDTCON
106h PORTB
107h CM1CON0
108h CM2CON0
109h CM2CON1
10Ah PCLATH
10Bh INTCON
—
—
—
WDTPS3
RB4
WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 221,214
RB7
RB6
RB5
RB3
—
RB2
C1R
C2R
—
RB1
RB0
xxxx xxxx
0000 -000
0000 -000
48,213
88,214
89,214
91,215
37,213
31,213
C1ON
C2ON
C1OUT
C2OUT
C1OE
C2OE
C1POL
C2POL
C2RSEL
C1CH1
C2CH1
T1GSS
C1CH0
C2CH0
—
MC1OUT MC2OUT C1RSEL
—
C2SYNC 0000 --10
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF(1)
EEDAT
EEADR
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEADR4
EEDAT3
EEADR3
EEDAT2
EEADR2
EEDAT1
EEADR1
EEDAT0 0000 0000 112,215
EEADR0 0000 0000 112,215
10Ch
10Dh
EEADR7 EEADR6 EEADR5
EEDATH5 EEDATH4
EEDATH3 EEDATH2 EEDATH1 EEDATH0
10Eh EEDATH
10Fh EEADRH
—
—
—
—
--00 0000 112,215
---- 0000 112,215
EEADRH4(2) EEADRH3 EEADRH2 EEADRH1 EEADRH0
—
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Note 1:
MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2:
PIC16F886/PIC16F887 only.
TABLE 2-4:
PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 3
180h INDF
181h OPTION_REG
182h PCL
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
37,213
30,214
37,213
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect Data Memory Address Pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
183h STATUS
184h FSR
PD
Z
DC
C
0001 1xxx
xxxx xxxx
0000 00-0
1111 1111
01-0 0-00
1111 1111
--11 1111
---0 0000
0000 000x
x--- x000
---- ----
29,213
37,213
93,215
48,214
160,215
40,215
99,215
37,213
31,213
113,215
111,215
185h SRCON
186h TRISB
SR1
TRISB7
ABDOVF
ANS7(2)
—
SR0
TRISB6
RCIDL
ANS6(2)
—
C1SEN
TRISB5
—
ANS5(2)
ANS13
—
C2REN
TRISB4
SCKP
PULSS
TRISB3
BRG16
ANS3
PULSR
TRISB2
—
—
FVREN
TRISB0
ABDEN
ANS0
TRISB1
WUE
187h BAUDCTL
188h ANSEL
189h ANSELH
18Ah PCLATH
18Bh INTCON
18Ch EECON1
18Dh EECON2
ANS4
ANS2
ANS10
ANS1
ANS9
ANS12
ANS11
ANS8
—
—
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
—
T0IE
INTE
—
RBIE
T0IF
INTF
WR
RBIF(1)
EEPGD
—
WRERR
WREN
RD
EEPROM Control Register 2 (not a physical register)
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Note 1:
MCLR and WDT Reset does not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2:
PIC16F884/PIC16F887 only.
DS41291D-page 28
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
