PIC16F882/883/884/886/887
TABLE 2-1:
PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
---0 0000
0000 000x
37,213
73,213
37,213
29,213
37,213
39,213
48,213
53,213
57,213
59,213
37,213
31,213
34,213
35,213
76,213
76,213
TMR0
PCL
Program Counter’s (PC) Least Significant Byte
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
PORTA(3)
PORTB(3)
PORTC(3)
PORTD(3,4)
PORTE(3)
RA7
RB7
RC7
RD7
—
RA6
RB6
RC6
RD6
—
RA5
RB5
RC5
RD5
—
RA4
RB4
RC4
RD4
—
RA3
RB3
RC3
RD3
RE3
RA2
RB2
RA1
RB1
RA0
RB0
RC2
RC1
RC0
RD2
RE2(4)
RD1
RE1(4)
RD0
RE0(4)
0Ah PCLATH
0Bh INTCON
0Ch PIR1
—
—
—
Write Buffer for upper 5 bits of Program Counter
GIE
—
PEIE
ADIF
C2IF
T0IE
RCIF
C1IF
INTE
TXIF
EEIF
RBIE
SSPIF
BCLIF
T0IF
INTF
TMR2IF
—
RBIF(1)
CCP1IF
ULPWUIF
TMR1IF -000 0000
0Dh PIR2
OSFIF
CCP2IF
0000 00-0
xxxx xxxx
xxxx xxxx
0Eh TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
10h
11h
12h
13h
14h
T1CON
T1GINV
Timer2 Module Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000
79,213
81,213
82,213
179,213
177,213
TMR2
0000 0000
T2CON
—
SSPBUF
SSPCON(2)
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
SSPM2
SSPM1
SSPM0
15h
16h
17h
18h
19h
CCPR1L
CCPR1H
CCP1CON
RCSTA
Capture/Compare/PWM Register 1 Low Byte (LSB)
Capture/Compare/PWM Register 1 High Byte (MSB)
126,213
126,213
124,213
P1M1
SPEN
P1M0
RX9
DC1B1
SREN
DC1B0
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000
ADDEN
FERR
OERR
RX9D
0000 000x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
159,213
151,213
156,213
126,213
TXREG
EUSART Transmit Data Register
EUSART Receive Data Register
1Ah RCREG
1Bh CCPR2L
Capture/Compare/PWM Register 2 Low Byte (LSB)
Capture/Compare/PWM Register 2 High Byte (MSB)
CCPR2H
1Ch
1Dh
126,214
CCP2CON
—
—
DC2B1
A/D Result Register High Byte
ADCS1 ADCS0 CHS3
DC2B0
CHS2
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000
125,214
99,214
1Eh ADRESH
xxxx xxxx
1Fh
ADCON0
CHS1
CHS0
GO/DONE
ADON
0000 0000
104,214
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Note 1:
MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2:
3:
4:
When SSPCON register bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed through the SSPMSK
register. See Registers • and 13-4 for more detail.
Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).
PIC16F884/PIC16F887 only.
DS41291D-page 26
Preliminary
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
