PIC16F882/883/884/886/887
TABLE 2-2:
PIC16F882/883/884/886/887 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
1111 1111
0000 0000
37,213
30,214
37,213
81h
OPTION_REG
PCL
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h
Program Counter’s (PC) Least Significant Byte
83h
84h
85h
86h
87h
88h
89h
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
1111 1111
1111 1111
29,213
37,213
39,214
48,214
53,214
57,214
59,214
37,213
31,213
Indirect Data Memory Address Pointer
TRISA
TRISB
TRISC
TRISD(3)
TRISE
TRISA7
TRISB7
TRISC7
TRISD7
—
TRISA6
TRISB6
TRISC6
TRISD6
—
TRISA5
TRISB5
TRISC5
TRISD5
—
TRISA4
TRISB4
TRISC4
TRISD4
—
TRISA3
TRISB3
TRISC3
TRISD3
TRISA2
TRISB2
TRISC2
TRISD2
TRISA1
TRISB1
TRISC1
TRISD1
TRISA0
TRISB0
TRISC0
TRISD0
TRISE3 TRISE2(3) TRISE1(3) TRISE0(3) ---- 1111
8Ah PCLATH
8Bh INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0000 000x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF(1)
8Ch PIE1
8Dh PIE2
8Eh PCON
—
OSFIE
—
ADIE
C2IE
RCIE
C1IE
TXIE
EEIE
SSPIE
BCLIE
—
CCP1IE
ULPWUIE
—
TMR2IE
—
TMR1IE
CCP2IE
BOR
-000 0000
0000 00-0
--01 --qq
-110 q000
---0 0000
0000 0000
1111 1111
0000 0000
32,214
33,214
36,214
62,214
66,214
177,214
81,214
185,214
—
ULPWUE SBOREN
POR
LTS
8Fh
90h
91h
92h
93h
OSCCON
OSCTUNE
SSPCON2
PR2
—
IRCF2
—
IRCF1
—
IRCF0
TUN4
OSTS
TUN3
RCEN
HTS
SCS
—
TUN2
PEN
TUN1
RSEN
TUN0
SEN
GCEN
ACKSTAT
ACKDT
ACKEN
Timer2 Period Register
Synchronous Serial Port (I2C mode) Address Register
SSPADD(2)
SSPMSK(2)
93h
94h
95h
96h
97h
98h
99h
MSK7
SMP
MSK6
CKE
MSK5
D/A
MSK4
P
MSK3
S
MSK2
R/W
MSK1
UA
MSK0
BF
1111 1111
0000 0000
1111 1111
0000 0000
0000 0000
0000 0010
0000 0000
0000 0000
0000 0000
204,214
185,214
49,214
SSPSTAT
WPUB
WPUB7
IOCB7
VREN
CSRC
BRG7
BRG15
PRSEN
WPUB6
IOCB6
VROE
TX9
WPUB5
IOCB5
VRR
WPUB4
IOCB4
VRSS
SYNC
BRG4
BRG12
PDC4
WPUB3
IOCB3
VR3
WPUB2
IOCB2
VR2
WPUB1
IOCB1
VR1
WPUB0
IOCB0
VR0
IOCB
49,214
VRCON
TXSTA
SPBRG
97,214
TXEN
BRG5
BRG13
PDC5
SENDB
BRG3
BRG11
PDC3
BRGH
BRG2
BRG10
PDC2
TRMT
BRG1
BRG9
PDC1
TX9D
BRG0
BRG8
PDC0
158,214
161,214
161,214
144,214
141,214
145,214
99,214
BRG6
BRG14
PDC6
9Ah SPBRGH
9Bh PWM1CON
9Ch ECCPAS
9Dh PSTRCON
9Eh ADRESL
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0
PSSBD1 PSSBD0 0000 0000
—
—
—
STRSYNC
STRD
STRC
STRB
STRA
---0 0001
xxxx xxxx
0-00 ----
A/D Result Register Low Byte
ADFM VCFG1
9Fh
ADCON1
—
VCFG0
—
—
—
—
105,214
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Note 1:
MCLR and WDT Reset do not affect the previous value data latch. The RBIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2:
3:
Accessible only when SSPCON register bits SSPM<3:0> = 1001.
PIC16F884/PIC16F887 only.
© 2007 Microchip Technology Inc.
Preliminary
DS41291D-page 27
MICROCHIP [ MICROCHIP ]
