PIC16F818/819
To ensure proper communication of the I2C Slave mode,
the TRIS bits (TRISx [SDA, SCL]) corresponding to the
I2C pins must be set to ‘1’. If any TRIS bits (TRISx<7:0>)
of the port containing the I2C pins (PORTx [SDA, SCL])
are changed in software during I2C communication
using a Read-Modify-Write instruction (BSF, BCF), then
the I2C mode may stop functioning properly and I2C
communication may suspend. Do not change any of the
TRISx bits (TRIS bits of the port containing the I2C pins)
using the instruction BSFor BCFduring I2C communica-
tion. If it is absolutely necessary to change the TRISx
bits during communication, the following method can be
used:
2
10.3 SSP I C Mode Operation
The SSP module in I2C mode fully implements all slave
functions, except general call support and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RB4/SCK/SCL pin, which is the clock (SCL) and the
RB1/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISB<4,1> bits.
EXAMPLE 10-1:
MOVF
IORLW
ANDLW
TRISC, W
0x18
B’11111001’
; Example for an 18-pin part such as the PIC16F818/819
; Ensures <4:3> bits are ‘11’
; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
MOVWF
TRISC
The SSP module functions are enabled by setting SSP
Enable bit, SSPEN (SSPCON<5>).
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
FIGURE 10-5:
SSP BLOCK DIAGRAM
(I2C™ MODE)
Internal
• I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled to support Firmware
Master mode
Data Bus
Read
Write
• I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled to support Firmware
Master mode
RB4/SCK/
SCL
SSPBUF Reg
• I2C Firmware Controlled Master mode with Start
and Stop bit interrupts enabled, slave is Idle
Shift
Clock
SSPSR Reg
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISB bits. Pull-up resistors
must be provided externally to the SCL and SDA pins
for proper operation of the I2C module.
Additional information on SSP I2C operation may be
found in the “PICmicro® Mid-Range MCU Family
Reference Manual” (DS33023).
RB1/
SDI/
SDA
MSb
LSb
Addr Match
Match Detect
SSPADD Reg
Set, Reset
S, P Bits
(SSPSTAT Reg)
Start and
Stop Bit Detect
The SSP module has five registers for I2C operation:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) – Not directly
accessible
• SSP Address Register (SSPADD)
DS39598E-page 76
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
