PIC16F818/819
10.3.2
MASTER MODE OPERATION
10.3.3
MULTI-MASTER MODE OPERATION
Master mode operation is supported in firmware using
interrupt generation on the detection of the Start and
Stop conditions. The Stop (P) and Start (S) bits are
cleared from a Reset or when the SSP module is dis-
abled. The Stop (P) and Start (S) bits will toggle based
on the Start and Stop conditions. Control of the I2C bus
may be taken when the P bit is set or the bus is Idle and
both the S and P bits are clear.
In Multi-Master mode operation, the interrupt genera-
tion on the detection of the Start and Stop conditions
allows the determination of when the bus is free. The
Stop (P) and Start (S) bits are cleared from a Reset or
when the SSP module is disabled. The Stop (P) and
Start (S) bits will toggle based on the Start and Stop
conditions. Control of the I2C bus may be taken when
bit P (SSPSTAT<4>) is set or the bus is Idle and both
the S and P bits clear. When the bus is busy, enabling
the SSP interrupt will generate the interrupt when the
Stop condition occurs.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISB<4,1> bit(s). The output level is always low,
irrespective of the value(s) in PORTB<4,1>. So when
transmitting data, a ‘1’ data bit must have the
TRISB<1> bit set (input) and a ‘0’ data bit must have
the TRISB<1> bit cleared (output). The same scenario
is true for the SCL line with the TRISB<4> bit. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I2C module.
In Multi-Master mode operation, the SDA line must be
monitored to see if the signal level is the expected
output level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISB<4,1>). There are two stages
where this arbitration can be lost:
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt if enabled):
• Address Transfer
• Data Transfer
• Start condition
When the slave logic is enabled, the Slave device
continues to receive. If arbitration was lost during the
address transfer stage, communication to the device
may be in progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data
transfer stage, the device will need to retransfer the
data at a later time.
• Stop condition
• Data transfer byte transmitted/received
Master mode operation can be done with either the
Slave mode Idle (SSPM3:SSPM0 = 1011) or with the
Slave mode active. When both Master mode operation
and Slave modes are used, the software needs to
differentiate the source(s) of the interrupt.
For more information on Multi-Master mode operation,
see AN578, “Use of the SSP Module in the I2C™
Multi-Master Environment” (DS00578).
For more information on Master mode operation, see
AN554, “Software Implementation of I2C™ Bus
Master” (DS00554).
TABLE 10-3: REGISTERS ASSOCIATED WITH I2C™ OPERATION
Value on
all other
Resets
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE TMR0IF INTF
RBIF
0000 000x 0000 000u
10Bh,18Bh
0Ch
8Ch
13h
PIR1
PIE1
—
—
ADIF
ADIE
—
—
—
—
SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
2
93h
SSPADD Synchronous Serial Port (I C™ mode) Address Register
14h
SSPCON
WCOL SSPOV SSPEN
CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
(1)
(1)
94h
SSPSTAT SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
1111 1111 1111 1111
86h
TRISB
PORTB Data Direction Register
Legend:
x= unknown, u= unchanged, -= unimplemented locations read as ‘0’.
Shaded cells are not used by SSP module in SPI™ mode.
2
Note 1: Maintain these bits clear in I C mode.
2004 Microchip Technology Inc.
DS39598E-page 79
MICROCHIP [ MICROCHIP ]
