欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16F688-I/ST 参数 Datasheet PDF下载

PIC16F688-I/ST图片预览
型号: PIC16F688-I/ST
PDF下载: 下载PDF文件 查看货源
内容描述: 14引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [14-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 202 页 / 3832 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16F688-I/ST的Datasheet PDF文件第155页浏览型号PIC16F688-I/ST的Datasheet PDF文件第156页浏览型号PIC16F688-I/ST的Datasheet PDF文件第157页浏览型号PIC16F688-I/ST的Datasheet PDF文件第158页浏览型号PIC16F688-I/ST的Datasheet PDF文件第160页浏览型号PIC16F688-I/ST的Datasheet PDF文件第161页浏览型号PIC16F688-I/ST的Datasheet PDF文件第162页浏览型号PIC16F688-I/ST的Datasheet PDF文件第163页  
PIC16F688  
TABLE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER  
AND BROWN-OUT RESET PARAMETERS  
Standard Operating Conditions (unless otherwise stated)  
Operating Temperature -40°C TA +125°C  
Param  
No.  
Sym  
TMCL  
Characteristic  
Min  
Typ†  
Max Units  
Conditions  
30  
MCLR Pulse Width (low)  
2
5
μs VDD = 5V, -40°C to +85°C  
μs VDD = 5V  
31  
32  
TWDT  
TOST  
Watchdog Timer Time-out  
Period (No Prescaler)  
10  
10  
16  
16  
29  
31  
ms VDD = 5V, -40°C to +85°C  
ms VDD = 5V  
Oscillation Start-up Timer  
Period(1, 2)  
1024  
TOSC (NOTE 3)  
33*  
34*  
TPWRT Power-up Timer Period  
40  
65  
140  
2.0  
ms  
TIOZ  
I/O High-impedance from  
MCLR Low or Watchdog Timer  
Reset  
μs  
35  
VBOR  
VHYST  
TBOR  
Brown-out Reset Voltage  
2.0  
50  
2.2  
V
(NOTE 4)  
36*  
37*  
Brown-out Reset Hysteresis  
mV  
Brown-out Reset Minimum  
Detection Period  
100  
μs VDD VBOR  
*
These parameters are characterized but not tested.  
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance  
only and are not tested.  
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values  
are based on characterization data for that particular oscillator type under standard operating conditions  
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-  
ation and/or higher than expected current consumption. All devices are tested to operate at “min” values  
with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time  
limit is “DC” (no clock) for all devices.  
2: By design.  
3: Period of the slower clock.  
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as  
possible. 0.1 μF and 0.01 μF values in parallel are recommended.  
© 2007 Microchip Technology Inc.  
DS41203D-page 157  
 复制成功!