PIC16F688
10.3.2
USART ASYNCHRONOUS
RECEIVER
10.3.3
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
The receiver block diagram is shown in Figure 10-5.
The data is received on the RC5/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter operating at 16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC. This mode would typi-
cally be used in RS-232 systems.
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
To set up an Asynchronous Reception:
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
1. Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
3. If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
7. The RCIF bit will be set when reception is
complete. The interrupt will be acknowledged if
the RCIE and GIE bits are set.
6. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
7. Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
8. Read the 8-bit received data by reading the
RCREG register.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
9. If any error occurred, clear the error by clearing
enable bit CREN.
10. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
FIGURE 10-5:
USART RECEIVE BLOCK DIAGRAM
CREN
OERR
FERR
RCIDL
x64 Baud Rate CLK
SPBRGH SPBRG
÷ 64
RSR Register
MSb
Stop (8)
LSb
0
START
BRG16
or
÷ 16
• • •
7
1
or
Baud Rate Generator
÷ 4
RX9
RC5/RX/DT pin
Pin Buffer
and Control
Data
Recovery
RX9D
RCREG Register
FIFO
SPEN
8
Interrupt
RCIF
RCIE
Data Bus
2004 Microchip Technology Inc.
Preliminary
DS41203B-page 89
MICROCHIP [ MICROCHIP ]
