PIC16F688
TABLE 2-4:
PIC16F688 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Value on
POR/BOD
Reset
Value on
all other
Resets(1)
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 3
180h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx
xxxx xxxx
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
190h
191h
192h
193h
194h
195h
196h
19Ah
19Bh
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
OPTION_REG
RAPU
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect Data Memory Address Pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
PCL
STATUS
FSR
TRISA
—
0000 0000
0000 0000
PD
Z
DC
C
0001 1xxx
000q quuu
xxxx xxxx
uuuu uuuu
—
—
TRISA5
TRISA4
TRISA3 TRISA2 TRISA1 TRISA0
TRISC3 TRISC2 TRISC1 TRISC0
--11 1111
--11 1111
Unimplemented
—
—
TRISC
—
—
—
TRISC5
TRISC4
--11 1111
--11 1111
Unimplemented
Unimplemented
—
—
—
—
—
PCLATH
INTCON
—
—
—
—
Write Buffer for upper 5 bits of Program Counter
INTE RAIE T0IF INTF
RAIF(2)
---0 0000
---0 0000
GIE
PEIE
T0IE
0000 0000
0000 0000
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend:
Note 1:
2:
- = Unimplemented locations read as ‘0’, u = unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon reset but will set again if the
mismatched exists.
DS41203B-page 12
Preliminary
2004 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
