PIC16F688
TABLE 2-3:
Addr
Bank 2
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
Legend:
Note 1:
2:
INDF
TMR0
PCL
STATUS
FSR
PORTA
—
PORTC
—
—
PCLATH
INTCON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Addressing this location uses contents of FSR to address data memory (not a physical
register)
Timer0 Module’s register
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
RA3
RA2
RA1
RA0
--xx xx00
—
RC5
RC4
RC3
RC2
RC1
RC0
--xx xx00
—
—
—
T0IE
Write Buffer for upper 5 bits of Program Counter
INTE
RAIE
T0IF
INTF
RAIF
(2)
PIC16F688 SPECIAL REGISTERS SUMMARY BANK 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOD
Reset
Value on
all other
Resets
(1)
Name
xxxx xxxx
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
--uu uuuu
—
--uu uuuu
—
—
---0 0000
0000 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Indirect Data Memory Address Pointer
—
—
RA5
RA4
Unimplemented
—
—
Unimplemented
Unimplemented
—
GIE
—
PEIE
---0 0000
0000 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
- = Unimplemented locations read as ‘0’, u = unchanged,
x
= unknown,
q
= value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
MCLR and WDT Reset does not affect the previous value data latch. The RAIF bit will be cleared upon reset but will set again if the
mismatched exists.
2004 Microchip Technology Inc.
Preliminary
DS41203B-page 11