PIC16F631/677/685/687/689/690
FIGURE 17-18:
A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
134
Q4
1 TCY
(1)
(TOSC/2)
131
130
A/D CLK
9
8
7
6
3
2
1
0
A/D Data
ADRES
NEW_DATA
1 TCY
OLD_DATA
ADIF
GO
DONE
Sampling Stopped
132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 17-16: A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C ≤ TA ≤ +125°C
Param
No.
Sym
Characteristic
A/D Clock Period
Min
Typ†
Max
Units
Conditions
130
TAD
1.5
—
—
—
—
μs TOSC-based, VREF ≥ 2.5V
μs TOSC-based, VREF full range
3.0*
130
TAD
A/D Internal RC
Oscillator Period
ADCS<1:0> = 11(RC mode)
μs At VDD = 2.5V
3.0*
2.0*
—
6.0
4.0
11
9.0*
6.0*
—
μs At VDD = 5.0V
131
132
TCNV Conversion Time
(not including
TAD Set GO bit to new data in A/D Result
register
Acquisition Time)(1)
(2)
TACQ Acquisition Time
11.5
—
—
—
μs
5*
μs The minimum time is the amplifier
settling time. This may be used if the
“new” input voltage has not changed
by more than 1 LSb (i.e., 4.1 mV @
4.096V) from the last sampled
voltage (as stored on CHOLD).
134
TGO
Q4 to A/D Clock
Start
—
TOSC/2
—
—
If the A/D clock source is selected as
RC, a time of TCY is added before
the A/D clock starts. This allows the
SLEEPinstruction to be executed.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.
2: See Table 9-1 for minimum conditions.
© 2007 Microchip Technology Inc.
DS41262D-page 253
MICROCHIP [ MICROCHIP ]
