PIC16F631/677/685/687/689/690
TABLE 17-12: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Typ† Max Units Conditions
70* TSSL2SCH, SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TSSL2SCL
71* TSCH
72* TSCL
SCK input high time (Slave mode)
SCK input low time (Slave mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
73* TDIV2SCH, Setup time of SDI data input to SCK edge
TDIV2SCL
74* TSCH2DIL, Hold time of SDI data input to SCK edge
TSCL2DIL
100
—
—
ns
75* TDOR
SDO data output rise time
3.0-5.5V
2.0-5.5V
—
—
—
10
—
—
—
—
—
Tcy
10
25
10
—
10
25
10
—
—
—
25
50
25
50
25
50
25
50
145
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
76* TDOF
SDO data output fall time
77* TSSH2DOZ SS↑ to SDO output high-impedance
78* TSCR
SCK output rise time
(Master mode)
3.0-5.5V
2.0-5.5V
79* TSCF
SCK output fall time (Master mode)
80* TSCH2DOV, SDO data output valid after
TSCL2DOV SCK edge
3.0-5.5V
2.0-5.5V
81* TDOV2SCH, SDO data output setup to SCK edge
TDOV2SCL
82* TSSL2DOV SDO data output valid after SS↓ edge
—
—
—
50
—
ns
ns
83* TSCH2SSH, SS ↑ after SCK edge
1.5TCY + 40
TSCL2SSH
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 17-16:
I2C™ BUS START/STOP BITS TIMING
SCL
SDA
91
93
90
92
Stop
Condition
Start
Condition
Note: Refer to Figure 17-3 for load conditions.
© 2007 Microchip Technology Inc.
DS41262D-page 249
MICROCHIP [ MICROCHIP ]
