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PIC16F685-I/SS 参数 Datasheet PDF下载

PIC16F685-I/SS图片预览
型号: PIC16F685-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 20引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 294 页 / 5272 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F631/677/685/687/689/690  
14.5.2  
WDT CONTROL  
14.5 Watchdog Timer (WDT)  
The WDTE bit is located in the Configuration Word  
register. When set, the WDT runs continuously.  
The WDT has the following features:  
• Operates from the LFINTOSC (31 kHz)  
• Contains a 16-bit prescaler  
When the WDTE bit in the Configuration Word register  
is set, the SWDTEN bit of the WDTCON register has no  
effect. If WDTE is clear, then the SWDTEN bit can be  
used to enable and disable the WDT. Setting the bit will  
enable it and clearing the bit will disable it.  
• Shares an 8-bit prescaler with Timer0  
• Time-out period is from 1 ms to 268 seconds  
• Configuration bit and software controlled  
WDT is cleared under certain conditions described in  
Table 14-7.  
The PSA and PS<2:0> bits of the OPTION register  
have the same function as in previous versions of the  
PIC16F631/677/685/687/689/690 Family of microcon-  
trollers. See Section 5.0 “Timer0 Module” for more  
information.  
14.5.1  
WDT OSCILLATOR  
The WDT derives its time base from the 31 kHz  
LFINTOSC. The LTS bit of the OSCCON register does  
not reflect that the LFINTOSC is enabled.  
The value of WDTCON is ‘---0 1000’ on all Resets.  
This gives a nominal time base of 17 ms.  
Note:  
When the Oscillator Start-up Timer (OST)  
is invoked, the WDT is held in Reset,  
because the WDT Ripple Counter is used  
by the OST to perform the oscillator delay  
count. When the OST count has expired,  
the WDT will begin counting (if enabled).  
FIGURE 14-9:  
WATCHDOG TIMER BLOCK DIAGRAM  
0
1
From TMR0 Clock Source  
Prescaler(1)  
16-bit WDT Prescaler  
8
PSA  
PS<2:0>  
To TMR0  
31 kHz  
LFINTOSC Clock  
WDTPS<3:0>  
1
0
PSA  
WDTE from the Configuration Word Register  
SWDTEN from WDTCON  
WDT Time-out  
Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.  
TABLE 14-7: WDT STATUS  
Conditions  
WDT  
WDTE = 0  
Cleared  
CLRWDTCommand  
Oscillator Fail Detected  
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK  
Exit Sleep + System Clock = XT, HS, LP  
Cleared until the end of OST  
DS41262D-page 208  
© 2007 Microchip Technology Inc.  
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