PIC16F631/677/685/687/689/690
FIGURE 14-10:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
(2)
TOST
INTF flag
(INTCON<1>)
Interrupt Latency(3)
GIE bit
(INTCON<7>)
Processor in
Sleep
Instruction Flow
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Inst(PC – 1)
Fetched
Instruction
Executed
Dummy Cycle
Dummy Cycle
Sleep
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
3: GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
This allows customers to manufacture boards with
14.7 Code Protection
unprogrammed devices and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.
Note:
The entire data EEPROM and Flash
program memory will be erased when the
code protection is switched from on to off.
See the “PIC12F6XX/16F6XX Memory
Programming Specification” (DS41204)
for more information.
The device is placed into a Program/Verify mode by
holding the RA0/AN0/C1IN+/ICSPDAT/ULPWU and
RA1/AN1/C12IN-/VREF/ICSPCLK pins low, while rais-
ing the MCLR (VPP) pin from VIL to VIHH. See the
“PIC12F6XX/16F6XX Memory Programming Specifi-
cation” (DS41204) for more information. RA0 becomes
the programming data and RA1 becomes the
programming clock. Both RA0 and RA1 are Schmitt
Trigger inputs in this mode.
14.8 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
After Reset, to place the device into Program/Verify
mode, the Program Counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending on
whether the command was a load or a read. For
complete details of serial programming, please refer to
the “PIC12F6XX/16F6XX Memory Programming
Specification” (DS41204).
14.9 In-Circuit Serial Programming
The PIC16F631/677/685/687/689/690 microcontrollers
can be serially programmed while in the end applica-
tion circuit. This is simply done with two lines for clock
and data and three other lines for:
A typical In-Circuit Serial Programming connection is
shown in Figure 14-11.
• power
• ground
• programming voltage
© 2007 Microchip Technology Inc.
DS41262D-page 211
MICROCHIP [ MICROCHIP ]
