PIC16F631/677/685/687/689/690
14.3.2
TMR0 INTERRUPT
14.3.3
PORTA/PORTB INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE (INTCON<5>)
bit. See Section 5.0 “Timer0 Module” for operation of
the Timer0 module.
An input change on PORTA or PORTB change sets the
RABIF (INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the RABIE (INTCON<3>)
bit. Plus, individual pins can be configured through the
IOCA or IOCB registers.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set. See
Section 4.2.3 “Interrupt-on-change” for
more information.
FIGURE 14-7:
INTERRUPT LOGIC
IOC-RA0
IOCA0
IOC-RA1
IOCA1
IOC-RA2
IOCA2
IOC-RA3
IOCA3
SSPIF
SSPIE
IOC-RA4
IOCA4
TXIF
TXIE
IOC-RA5
IOCA5
RCIF
RCIE
(1)
Wake-up (If in Sleep mode)
IOC-RB4
IOCB4
T0IF
T0IE
TMR2IF
TMR2IE
Interrupt to CPU
INTF
INTE
RABIF
IOC-RB5
IOCB5
TMR1IF
TMR1IE
IOC-RB6
IOCB6
RABIE
C1IF
C1IE
PEIE
GIE
IOC-RB7
IOCB7
C2IF
C2IE
ADIF
ADIE
EEIF
EEIE
Note 1: Some peripherals depend upon the system
clock for operation. Since the system clock is
suspended during Sleep, these peripherals
will not wake the part from Sleep. See
OSFIF
OSFIE
CCP1IF
CCP1IE
Section 14.6.1 “Wake-up from Sleep”.
© 2007 Microchip Technology Inc.
DS41262D-page 205
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