欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC16F685-I/SS 参数 Datasheet PDF下载

PIC16F685-I/SS图片预览
型号: PIC16F685-I/SS
PDF下载: 下载PDF文件 查看货源
内容描述: 20引脚基于闪存的8位CMOS微控制器采用纳瓦技术 [20-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器
文件页数/大小: 294 页 / 5272 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC16F685-I/SS的Datasheet PDF文件第193页浏览型号PIC16F685-I/SS的Datasheet PDF文件第194页浏览型号PIC16F685-I/SS的Datasheet PDF文件第195页浏览型号PIC16F685-I/SS的Datasheet PDF文件第196页浏览型号PIC16F685-I/SS的Datasheet PDF文件第198页浏览型号PIC16F685-I/SS的Datasheet PDF文件第199页浏览型号PIC16F685-I/SS的Datasheet PDF文件第200页浏览型号PIC16F685-I/SS的Datasheet PDF文件第201页  
PIC16F631/677/685/687/689/690  
REGISTER 14-1: CONFIG: CONFIGURATION WORD REGISTER  
Reserved  
bit 13  
Reserved  
FCMEN  
PWRTE  
IESO  
BOREN1(1)  
BOREN0(1)  
CPD(2  
bit 7  
CP(3)  
MCLRE(4)  
WDTE  
FOSC2  
FOSC1  
FOSC0  
bit 0  
bit 6  
Legend:  
R = Readable bit  
W = Writable bit  
‘1’ = Bit is set  
P = Programmable’  
‘0’ = Bit is cleared  
U = Unimplemented  
bit, read as ‘0’  
-n = Value at POR  
x = Bit is unknown  
bit 13-12  
bit 11  
Reserved: Reserved bits. Do Not Use.  
FCMEN: Fail-Safe Clock Monitor Enabled bit  
1= Fail-Safe Clock Monitor is enabled  
0= Fail-Safe Clock Monitor is disabled  
bit 10  
IESO: Internal External Switchover bit  
1= Internal External Switchover mode is enabled  
0= Internal External Switchover mode is disabled  
bit 9-8  
BOREN<1:0>: Brown-out Reset Selection bits(1)  
11= BOR enabled  
10= BOR enabled during operation and disabled in Sleep  
01= BOR controlled by SBOREN bit of the PCON register  
00= BOR disabled  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2-0  
CPD: Data Code Protection bit(2)  
1= Data memory code protection is disabled  
0= Data memory code protection is enabled  
CP: Code Protection bit(2)  
1= Program memory code protection is disabled  
0= Program memory code protection is enabled  
MCLRE: MCLR Pin Function Select bit(3)  
1= MCLR pin function is MCLR  
0= MCLR pin function is digital input, MCLR internally tied to VDD  
PWRTE: Power-up Timer Enable bit  
1= PWRT disabled  
0= PWRT enabled  
WDTE: Watchdog Timer Enable bit  
1= WDT enabled  
0= WDT disabled  
FOSC<2:0>: Oscillator Selection bits  
111=  
110=  
101=  
RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN  
RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN  
INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on  
RA5/OSC1/CLKIN  
100=  
INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on  
RA5/OSC1/CLKIN  
011=  
010=  
001=  
000=  
EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN  
HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN  
XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN  
LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN  
Note 1:  
Enabling Brown-out Reset does not automatically enable Power-up Timer.  
The entire data EEPROM will be erased when the code protection is turned off.  
The entire program memory will be erased when the code protection is turned off.  
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.  
2:  
3:  
4:  
© 2007 Microchip Technology Inc.  
DS41262D-page 195  
 复制成功!