PIC16F631/677/685/687/689/690
FIGURE 13-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX-1
Master device
asserts clock
CKP
Master device
deasserts clock
WR
SSPCON
TABLE 13-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION(1)
Value on
all other
Resets
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh/
10Bh/18Bh
INTCON
GIE
—
PEIE
ADIF
T0IE
INTE
TXIF
RABIE
SSPIF
T0IF
INTF
RABIF
0000 000x
0000 000x
0Ch
13h
14h
86h
PIR1
RCIF
CCP1IF
TMR2IF
TMR1IF -000 0000
-000 0000
uuuu uuuu
0000 0000
1111 ----
SSPBUF
SSPCON
TRISB
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
WCOL
SSPOV
TRISB6
SSPEN
TRISB5
CKP
SSPM3
—
SSPM2
—
SSPM1
—
SSPM0
—
0000 0000
1111 ----
TRISB7
TRISB4
93h
94h
8Ch
SSPMSK(2)
SSPSTAT
PIE1
MSK7
SMP(3)
—
MSK6
CKE(3)
ADIE
MSK5
D/A
MSK4
P
MSK3
S
MSK2
R/W
MSK1
UA
MSK0
BF
1111 1111
0000 0000
1111 1111
0000 0000
-000 0000
RCIE
TXIE
SSPIE
CCP1IE
TMR2IF
TMR1IF -000 0000
Legend:
Note 1:
2:
– = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the SSP module.
PIC16F687/PIC16F689/PIC16F690 only.
SSPMSK register (Register 13-3) can be accessed by reading or writing to SSPADD register with bits SSPM<3:0> = 1001.
See Registers 13-2 and 13-3 for more details.
3:
Maintain these bits clear.
DS41262D-page 192
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
