PIC16F631/677/685/687/689/690
If the system clock is changed during an active receive
12.3 EUSART Baud Rate Generator
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCTL register selects 16-bit
mode.
EXAMPLE 12-1:
CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
The SPBRGH, SPBRG register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCTL register. In
Synchronous mode, the BRGH bit is ignored.
FOSC
--------------------------------------------------------------------
=
Desired Baud Rate
64([SPBRGH:SPBRG] + 1)
Solving for SPBRGH:SPBRG:
FOSC
---------------------------------------------
Table 12-3 contains the formulas for determining the
baud rate. Example 12-1 provides a sample calculation
for determining the baud rate and baud rate error.
Desired Baud Rate
---------------------------------------------
X =
=
– 1
64
16000000
-----------------------
9600
64
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 12-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
-----------------------
– 1
= [25.042] = 25
16000000
64(25 + 1)
--------------------------
=
Calculated Baud Rate
= 9615
Writing a new value to the SPBRGH, SPBRG register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
Calc. Baud Rate – Desired Baud Rate
--------------------------------------------------------------------------------------------
Error =
Desired Baud Rate
(9615 – 9600)
----------------------------------
=
= 0.16%
9600
TABLE 12-3: BAUD RATE FORMULAS
Configuration Bits
Baud Rate Formula
BRG/EUSART Mode
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n+1)]
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend:
x= Don’t care, n = value of SPBRGH, SPBRG register pair
TABLE 12-4: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCTL ABDOVF RCIDL
—
SCKP
CREN
BRG4
BRG12
SYNC
BRG16
ADDEN
BRG3
—
WUE
OERR
BRG1
BRG9
TRMT
ABDEN 01-0 0-00 01-0 0-00
RCSTA
SPBRG
SPBRGH
TXSTA
SPEN
BRG7
BRG15
CSRC
RX9
BRG6
BRG14
TX9
SREN
BRG5
BRG13
TXEN
FERR
BRG2
BRG10
BRGH
RX9D
BRG0
BRG8
TX9D
0000 000x 0000 000x
0000 0000 0000 0000
0000 0000 0000 0000
0000 0010 0000 0010
BRG11
SENDB
Legend:
x= unknown, – = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
© 2007 Microchip Technology Inc.
DS41262D-page 161
MICROCHIP [ MICROCHIP ]
