PIC16F631/677/685/687/689/690
and SPBRG registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
12.3.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Section 12.3.2
“Auto-Wake-up
on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
Setting the ABDEN bit of the BAUDCTL register starts
the auto-baud calibration sequence (Figure 12-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 12-6. The fifth rising edge will occur on the RX
pin at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH, SPBRG register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag
is set. The value in the RCREG needs to be read to
clear the RCIF interrupt. RCREG content should be
discarded. When calibrating for modes that do not use
the SPBRGH register the user can verify that the
SPBRG register did not overflow by checking for 00h in
the SPBRGH register.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence,
accuracy,
to
achieve
maximum
from the
subtract
1
SPBRGH:SPBRG register pair.
TABLE 12-6:
BRG COUNTER CLOCK RATES
BRG Base
Clock
BRG ABD
Clock
BRG16 BRGH
0
0
0
1
FOSC/64
FOSC/16
FOSC/512
FOSC/128
1
1
0
1
FOSC/16
FOSC/4
FOSC/128
FOSC/32
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 12-6. During ABD,
both the SPBRGH and SPBRG registers are used as a
16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
Note:
During the ABD sequence, SPBRG and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 12-6:
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
0000h
001Ch
BRG Value
Edge #1
bit 1
Edge #2
bit 3
Edge #3
bit 5
Edge #4
bit 7
bit 6
Edge #5
Stop bit
RX pin
Start
bit 0
bit 2
bit 4
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
XXh
XXh
1Ch
00h
SPBRG
SPBRGH
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
© 2007 Microchip Technology Inc.
DS41262D-page 165
MICROCHIP [ MICROCHIP ]
