PIC16F630/676
When the A/D clock source is something other than
RC, a SLEEPinstruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
7.3
A/D Operation During SLEEP
The A/D converter module can operate during SLEEP.
This requires the A/D clock source to be set to the
internal oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEPinstruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from SLEEP.
If the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
7.4
Effects of RESET
A device RESET forces all registers to their RESET
state. Thus, the A/D module is turned off and any
pending conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
TABLE 7-2:
SUMMARY OF A/D REGISTERS
Value on
Value on:
POR, BOD
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
05h
07h
PORTA
PORTC
—
—
—
PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 --xx xxxx --uu uuuu
PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 --xx xxxx --uu uuuu
—
0Bh, 8Bh INTCON
GIE
EEIF
PEIE
ADIF
T0IE
—
INTE
—
RAIE
CMIF
T0IF
—
INTF
—
RAIF
TMR1IF 00-- 0--0 00-- 0--0
xxxx xxxx uuuu uuuu
ADON 00-0 0000 00-0 0000
0000 0000 0000 000u
0Ch
1Eh
1Fh
85h
87h
8Ch
91h
9Eh
9Fh
PIR1
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result
ADCON0
TRISA
TRISC
PIE1
ADFM
—
VCFG
—
—
CHS2
CHS1
CHS0
GO
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111
—
—
EEIE
ANS7
ADIE
ANS6
—
—
CMIE
ANS3
—
—
TMR1IE 00-- 0--0 00-- 0--0
ANS0 1111 1111 1111 1111
ANSEL
ANS5
ANS4
ANS2
ANS1
ADRESL Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result xxxx xxxx uuuu uuuu
ADCON1 ADCS2 ADCS1 ADCS0 -000 ---- -000 ----
—
—
—
—
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D converter module.
DS40039E-page 48
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
