PIC16F630/676
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
8.3
READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>), as shown in Example 8-1. The data
is available, in the very next cycle, in the EEDATA
register. Therefore, it can be read in the next
instruction. EEDATA holds this value until another read,
or until it is written to by the user (during a write
operation).
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR<7>) register must be cleared by software.
8.5
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (see Example 8-3) to the
desired value to be written.
EXAMPLE 8-1:
DATA EEPROM READ
bsf
STATUS,RP0
;Bank 1
movlw CONFIG_ADDR
movwf EEADR
;
;Address to read
;EE Read
EXAMPLE 8-3:
WRITE VERIFY
bsf
EECON1,RD
EEDATA,W
movf
;Move data to W
bcf
:
STATUS,RP0
;Bank 0
;Any code
bsf
movf
STATUS,RP0
;Bank 1 READ
8.4
WRITING TO THE EEPROM DATA
MEMORY
EEDATA,W
;EEDATA not changed
;from previous write
;YES, Read the
bsf
EECON1,RD
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 8-2.
;value written
xorwf EEDATA,W
btfss STATUS,Z
;Is data the same
;No, handle error
;Yes, continue
goto
:
WRITE_ERR
EXAMPLE 8-2:
DATA EEPROM WRITE
8.5.1
USING THE DATA EEPROM
bsf
bsf
bcf
STATUS,RP0
EECON1,WREN
INTCON,GIE
;Bank 1
The Data EEPROM is a high-endurance, byte addres-
sable array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specifications D120 or D120A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
FLASH program memory.
;Enable write
;Disable INTs
movlw 55h
;Unlock write
movwf EECON2
movlw AAh
;
;
movwf EECON2
;
bsf
bsf
EECON1,WR
INTCON,GIE
;Start the write
;Enable INTS
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
8.6
PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• brown-out
• power glitch
• software malfunction
© 2007 Microchip Technology Inc.
DS40039E-page 51
MICROCHIP [ MICROCHIP ]
