PIC16F630/676
3.2.3.3
RA2/AN2/T0CKI/INT/COUT
3.2.3.4
RA3/MCLR/VPP
Figure 3-2 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following:
Figure 3-3 shows the diagram for this pin. The RA3 pin
is configurable to function as one of the following:
• a general purpose I/O
• a general purpose input
• as Master Clear Reset
• an analog input for the A/D (PIC16F676 only)
• a digital output from the comparator
• the clock input for TMR0
FIGURE 3-3:
BLOCK DIAGRAM OF RA3
• an external edge triggered interrupt
Data Bus
MCLRE
I/O pin
RESET
FIGURE 3-2:
BLOCK DIAGRAM OF RA2
Analog
RD
VSS
TRISA
Input Mode
Data Bus
D
MCLRE
VSS
Q
Q
VDD
RD
PORTA
WR
WPUA
CK
Weak
D
Q
Q
Q
D
CK
WR
IOCA
RAPU
Q
RD
WPUA
EN
Analog
COUT
Input
RD
IOCA
Enable
Mode
D
VDD
D
Q
Q
EN
WR
PORTA
CK
Interrupt-on-Change
COUT
1
0
RD PORTA
I/O pin
D
Q
Q
WR
TRISA
CK
VSS
Analog
Input Mode
RD
TRISA
RD
PORTA
D
Q
Q
Q
D
D
CK
WR
IOCA
EN
RD
IOCA
Q
EN
Interrupt-on-Change
RD PORTA
To TMR0
To INT
To A/D Converter
© 2007 Microchip Technology Inc.
DS40039E-page 23
MICROCHIP [ MICROCHIP ]
