PIC16F630/676
3.2.3.5
RA4/AN3/T1G/OSC2/CLKOUT
3.2.3.6
RA5/T1CKI/OSC1/CLKIN
Figure 3-4 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
Figure 3-5 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
• an analog input for the A/D (PIC16F676 only)
• a TMR1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 3-5:
BLOCK DIAGRAM OF RA5
FIGURE 3-4:
BLOCK DIAGRAM OF RA4
INTOSC
Mode
Analog
TMR1LPEN(1)
VDD
Input Mode
CLK(1)
Data Bus
D
Modes
VDD
Q
Q
Data Bus
D
Q
Q
WR
CK
Weak
WR
WPUA
CK
WPUA
Weak
RAPU
RD
RAPU
RD
WPUA
WPUA
Oscillator
Circuit
Oscillator
Circuit
OSC1
OSC2
VDD
VDD
D
Q
Q
CLKOUT
Enable
WR
PORTA
CK
FOSC/4
1
0
D
Q
Q
I/O pin
I/O pin
WR
CK
D
Q
Q
PORTA
CLKOUT
Enable
WR
TRISA
CK
VSS
VSS
D
Q
Q
INTOSC/
RC/EC(2)
INTOSC
Mode
RD
TRISA
WR
TRISA
CK
CLKOUT
Enable
(1)
RD
PORTA
RD
TRISA
Analog
Input Mode
D
Q
Q
RD
PORTA
Q
Q
D
CK
WR
IOCA
D
Q
Q
EN
Q
D
D
RD
IOCA
CK
WR
IOCA
EN
D
RD
IOCA
EN
Q
Interrupt-on-Change
EN
Interrupt-on-Change
RD PORTA
RD PORTA
To TMR1 or CLKGEN
To TMR1 T1G
To A/D Converter
Note 1: Timer1 LP Oscillator enabled.
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
2: When using Timer1 with LP oscillator, the Schmitt
Enable.
Trigger is by-passed.
2: With CLKOUT option.
DS40039E-page 24
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
