PIC16F5X
FIGURE 3-2:
PIC16F57/PIC16F59
PROGRAM MEMORY MAP
AND STACK
3.0
MEMORY ORGANIZATION
PIC16F5X memory is organized into program memory
and data memory. For the PIC16F57 and PIC16F59,
which have more than 512 words of program memory,
a paging scheme is used. Program memory pages are
accessed using one or two STATUS register bits. For
the PIC16F57 and PIC16F59, which have a data mem-
ory register file of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Selection Register (FSR).
PC<10:0>
11
CALL, RETLW
Stack Level 1
Stack Level 2
000h
On-chip Program
0FFh
Memory (Page 0)
100h
3.1
Program Memory Organization
1FFh
200h
The PIC16F54 has a 9-bit Program Counter (PC)
capable of addressing a 512 x 12 program memory
space (Figure 3-1). The PIC16F57 and PIC16F59 have
an 11-bit Program Counter capable of addressing a 2K
x 12 program memory space (Figure 3-2). Accessing a
location above the physically implemented address will
cause a wraparound.
On-chip Program
2FFh
Memory (Page 1)
300h
3FFh
400h
On-chip Program
4FFh
Memory (Page 2)
500h
A NOPat the Reset vector location will cause a restart
at location 000h. The Reset vector for the PIC16F54 is
at 1FFh. The Reset vector for the PIC16F57 and
PIC16F59 is at 7FFh. See Section 3.5 “Program
Counter” for additional information using CALL and
GOTOinstructions.
5FFh
600h
On-chip Program
6FFh
Memory (Page 3)
700h
Reset Vector
7FFh
FIGURE 3-1:
PIC16F54 PROGRAM
MEMORY MAP AND
STACK
PC<8:0>
9
CALL, RETLW
Stack Level 1
Stack Level 2
000h
On-chip
Program
Memory
0FFh
100h
Reset Vector
1FFh
© 2007 Microchip Technology Inc.
DS41213D-page 13
MICROCHIP [ MICROCHIP ]
